Programmable via devices with metal/semiconductor via links and fabrication methods thereof

    公开(公告)号:US09812393B2

    公开(公告)日:2017-11-07

    申请号:US14867341

    申请日:2015-09-28

    CPC classification number: H01L23/5256 H01L23/5226

    Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

    Programmable devices with current-facilitated migration and fabrication methods

    公开(公告)号:US09691497B2

    公开(公告)日:2017-06-27

    申请号:US14867331

    申请日:2015-09-28

    CPC classification number: G11C17/16 H01L23/5256 H01L29/0673 H01L29/785

    Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.

    Fabrication methods for multi-layer semiconductor structures
    17.
    发明授权
    Fabrication methods for multi-layer semiconductor structures 有权
    多层半导体结构的制作方法

    公开(公告)号:US09502301B2

    公开(公告)日:2016-11-22

    申请号:US14730614

    申请日:2015-06-04

    Abstract: Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.

    Abstract translation: 提供了制造多层半导体结构的方法。 所述方法包括例如:在衬底上提供第一层和第二层,第一层包括第一金属,第二层包括第二金属,其中第二层设置在第一层和第一金属之上, 第二种金属是不同的金属; 以及退火所述第一层,所述第二层和所述衬底以使所述第一层的所述第一金属的至少一部分反应以形成第一反应层和所述第二层的所述第二金属的至少一部分,以形成第二层 其中第一反应层或第二反应层中的至少一个包含第一金属的第一金属硅化物或第二金属的第二金属硅化物中的至少一种。

    Semiconductor structure with anti-efuse device

    公开(公告)号:US09754903B2

    公开(公告)日:2017-09-05

    申请号:US14926880

    申请日:2015-10-29

    CPC classification number: H01L23/62 H01L23/5252

    Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

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