公开(公告)号：US10326007B2

公开(公告)日：2019-06-18

申请号：US16026820

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Timothy J. McArdle ,  Judson Robert Holt

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.

公开(公告)号：US10204984B1

公开(公告)日：2019-02-12

申请号：US15667376

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Matthew W. Stoker ,  Judson R. Holt ,  Timothy J. McArdle ,  Annie Lévesque

IPC: H01L29/49 ,  H01L29/06 ,  H01L27/108 ,  H01L21/02 ,  H01L29/423

Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.

公开(公告)号：US20190027370A1

公开(公告)日：2019-01-24

申请号：US15653594

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Hyun-Jin Cho ,  Anil Kumar ,  Timothy J. McArdle

IPC: H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

Abstract: Methods of forming a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a cavity extending through the semiconductor fin and into a substrate fin underlying the semiconductor fin. After the cavity is formed, the semiconductor fin is etched selective to the substrate fin with a second etching process to widen a portion of the cavity.

公开(公告)号：US20170117387A1

公开(公告)日：2017-04-27

申请号：US14921434

申请日：2015-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC: H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

公开(公告)号：US20170033181A1

公开(公告)日：2017-02-02

申请号：US14810574

申请日：2015-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy J. McArdle ,  Judson R. Holt ,  Bharat V. Krishnan ,  Jody A. Fronheiser

IPC: H01L29/10 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/1054 ,  H01L21/02107 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.

Abstract translation: 本文中公开的一种说明性方法包括在衬底翅片腔中单独形成不同半导体材料的交替层，以在凹陷衬底鳍上方形成多层鳍，其中形成不同半导体材料的各层 到最终厚度小于所形成的不同半导体材料的层的临界厚度，使绝缘材料层凹陷，以便将多层鳍片的至少一部分暴露在层的凹陷的上表面上方 绝缘材料并围绕暴露的多层鳍片的至少一部分形成栅极结构。

公开(公告)号：US20180190768A1

公开(公告)日：2018-07-05

申请号：US15848591

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dina H. Triyoso ,  Timothy J. McArdle ,  Judson R. Holt ,  Amy L. Child ,  George R. Mulfinger

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76264 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/78684

Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.

公开(公告)号：US09953873B2

公开(公告)日：2018-04-24

申请号：US15163313

申请日：2016-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bhupesh Chandra ,  Claude Ortolland ,  Gregory G. Freeman ,  Viorel Ontalus ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Paul Chang

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/32 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/32 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/6656

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

公开(公告)号：US09812453B1

公开(公告)日：2017-11-07

申请号：US15431334

申请日：2017-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Lakshmanan H. Vanamurthy ,  Scott Beasor ,  Timothy J. McArdle ,  Judson R. Holt ,  Hao Zhang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.

公开(公告)号：US09722045B2

公开(公告)日：2017-08-01

申请号：US14921434

申请日：2015-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

公开(公告)号：US09698226B1

公开(公告)日：2017-07-04

申请号：US15095376

申请日：2016-04-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy J. McArdle ,  Judson R. Holt ,  Junli Wang

IPC: H01L29/04 ,  H01L29/161 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/04 ,  H01L29/045 ,  H01L29/10 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.