公开(公告)号：US08667430B1

公开(公告)日：2014-03-04

申请号：US13774822

申请日：2013-02-22

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G03F1/00 ,  G06F17/11 ,  G06F17/13

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0002 ,  G06F17/11 ,  G06F17/13 ,  G06F19/00 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. Designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern. Generating the second, updated DSA directing pattern includes linearizing a self-consistent field theory equation.

Abstract translation: 制造集成电路的方法包括设计用于在半导体衬底上的光致抗蚀剂层中形成预图案开口的光学光掩模，其中光致抗蚀剂层和预图案开口涂覆有经历定向自我的自组装材料 - 组装（DSA）以形成DSA模式。 设计光学光掩模包括使用计算系统，输入DSA目标图案，并使用计算系统，将DSA模型应用于DSA目标图案以生成第一DSA定向图案。 此外，设计光学光掩模的步骤包括使用计算系统，计算DSA目标模式和DSA指导模式之间的残差，并使用计算系统，将DSA模型应用于第一DSA指导模式，并且剩余生成 第二个更新的DSA指导模式。 生成第二个更新的DSA指导模式包括线性化自相一致的场理论方程。

公开(公告)号：US09286434B2

公开(公告)日：2016-03-15

申请号：US14285739

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yi Zou ,  Wei-Long Wang ,  Azat Latypov ,  Tamer Coskun

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F7/0002 ,  G06F17/5068 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括生成用于形成覆盖半导体衬底的DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括在设计布局中标识DSA目标图案的位置。 DSA目标模式被分组成包括第一组的组，并且围绕第一组定义第一组边界。 所述方法还包括确定到所述第一组边界的相邻DSA目标图案是否是距离在所述第一组边界内的相邻DSA目标图案至少预定的最小保持距离。 该方法还包括确定第一组中的DSA目标模式是否兼容DSA。 使用第一组边界生成输出掩模图案。

公开(公告)号：US20150235839A1

公开(公告)日：2015-08-20

申请号：US14185491

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Tamer Coskun ,  Wei-Long Wang ,  Azat Latypov ,  Yi Zou

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0274 ,  H01L21/308

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成覆盖在半导体衬底上的辅助抗蚀刻填充形貌特征，并且使用光掩模来定义辅助耐蚀刻填充约束阱。 光掩模定义了辅助的可光刻印刷的掩模特征。 将嵌段共聚物沉积到辅助抗蚀填充密封阱中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 辅助抗蚀刻填充形貌特征指示耐腐蚀相以在辅助耐蚀刻填充密封阱中形成耐蚀刻塞。

公开(公告)号：US09053923B2

公开(公告)日：2015-06-09

申请号：US14072149

申请日：2013-11-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Edward Teoh Kah Ching ,  He Yi

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/027

CPC classification number: H01L21/0271 ,  G03F7/0002 ,  H01L21/308 ,  H01L21/3081

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成覆盖半导体衬底的耐蚀刻填充控制形貌特征。 抗蚀刻填充控制形貌特征限定了耐蚀刻填充控制密封阱。 将嵌段共聚物沉积到耐蚀刻填充控制密封阱中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻填充控制形状特征指示耐蚀刻相，以在耐蚀刻填充控制密封阱中形成耐蚀刻塞。

公开(公告)号：US20150126034A1

公开(公告)日：2015-05-07

申请号：US14072149

申请日：2013-11-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Edward Teoh Kah Ching ,  He Yi

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0271 ,  G03F7/0002 ,  H01L21/308 ,  H01L21/3081

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成覆盖半导体衬底的耐蚀刻填充控制形貌特征。 抗蚀刻填充控制形貌特征限定了耐蚀刻填充控制密封阱。 将嵌段共聚物沉积到耐蚀刻填充控制密封阱中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻填充控制形状特征指示耐蚀刻相，以在耐蚀刻填充控制密封阱中形成耐蚀刻塞。

公开(公告)号：US09023730B1

公开(公告)日：2015-05-05

申请号：US14072164

申请日：2013-11-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Yi Zou ,  Vito Dai

IPC: H01L21/311 ,  G06F17/50 ,  H01L21/027 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/0273

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating an e-beam pattern for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the e-beam pattern includes using a computing system, inputting a DSA target pattern. Using the computing system, the DSA target pattern, a DSA model, and an EBPC model, an output EBPCed pattern is produced for an e-beam writer to write on a resist layer that overlies the semiconductor substrate.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括产生用于在半导体衬底上形成DSA定向图案的电子束图案。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成电子束图案包括使用计算系统，输入DSA目标图案。 使用计算系统，DSA目标模式，DSA模型和EBPC模型，产生用于电子束写入器写入覆盖在半导体衬底上的抗蚀剂层上的输出EBPC模式。

公开(公告)号：US10153162B2

公开(公告)日：2018-12-11

申请号：US15284773

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-Han Kim ,  Wenhui Wang ,  Azat Latypov ,  Tamer Coskun, Jr. ,  Lei Sun

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/66

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

公开(公告)号：US09170501B2

公开(公告)日：2015-10-27

申请号：US13936924

申请日：2013-07-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Yi Zou ,  Vito Dai

IPC: G06F17/50 ,  G03F7/20

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0002

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes using a computing system, inputting a DSA target pattern and an initial pattern. An output mask writer pattern is produced from the initial pattern using the computing system, the DSA target pattern, a DSA model, an OPC model, and a MPC model. The output mask writer pattern is for a mask writer to write on the photomask.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括产生用于在半导体衬底上形成DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括使用计算系统，输入DSA目标图案和初始图案。 使用计算系统，DSA目标模式，DSA模型，OPC模型和MPC模型从初始模式生成输出掩码写入器模式。 输出掩码写入器模式用于掩码写入器写入光掩模。

公开(公告)号：US20150242555A1

公开(公告)日：2015-08-27

申请号：US14189465

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei-Long Wang ,  Azat Latypov ,  Yi Zou ,  Tamer Coskun

IPC: G06F17/50 ,  H01L21/311 ,  H01L21/027

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  H01L21/0271 ,  H01L21/0274 ,  H01L21/31133

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes inputting DSA target patterns. The DSA target patterns are grouped into groups including a first group and a group boundary is defined around the first group as an initial OPC mask pattern. A circle target is generated around each of the DSA target patterns in the first group to define a merged circle target boundary. The initial OPC mask pattern is adjusted and/or iteratively updated using the merged circle target boundary to generate an output final OPC mask pattern.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括生成用于形成覆盖半导体衬底的DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括输入DSA目标图案。 DSA目标图案被分组成包括第一组的组，并且组边界围绕第一组被定义为初始OPC掩模模式。 围绕第一组中的每个DSA目标图案生成圆目标以定义合并的圆目标边界。 使用合并的圆目标边界来调整和/或迭代地更新初始OPC掩模图案以生成输出的最终OPC掩模图案。