公开(公告)号：US10249590B2

公开(公告)日：2019-04-02

申请号：US15614850

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Sebastian T. Ventrone ,  Richard S. Graf

IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L25/065

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.

公开(公告)号：US10013519B2

公开(公告)日：2018-07-03

申请号：US15270598

申请日：2016-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Jeanne P. Bickford

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.

公开(公告)号：US09952500B2

公开(公告)日：2018-04-24

申请号：US15239072

申请日：2016-08-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Arun S. Mampazhy

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first pattern positioned adjacent to a second pattern, wherein an OPC modeling rule of the IC design layout prohibits the first pattern from being adjusted, and wherein the second pattern does not reduce a printability metric of the first pattern; adjusting the design of the second pattern to reduce at least one printing error in the first pattern, wherein a functionality of the second pattern in the IC design layout is unchanged after the adjusting; and implementing OPC on the IC design layout including the target region with the adjusted second pattern therein.

公开(公告)号：US20180019227A1

公开(公告)日：2018-01-18

申请号：US15210403

申请日：2016-07-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sebastian T. Ventrone ,  Sudeep Mandal

IPC: H01L25/065 ,  G11C15/04 ,  G11C15/06

CPC classification number: H01L25/0657 ,  G11C15/04 ,  G11C15/06 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06572

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.

公开(公告)号：US20170324015A1

公开(公告)日：2017-11-09

申请号：US15147595

申请日：2016-05-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Richard S. Graf

IPC: H01L35/10 ,  H01L35/34 ,  H01L23/38

CPC classification number: H01L35/10 ,  H01L23/38 ,  H01L35/34

Abstract: Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via.

公开(公告)号：US09585257B2

公开(公告)日：2017-02-28

申请号：US14668031

申请日：2015-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  David J. Russell

IPC: H05K3/02 ,  H05K3/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/373 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H01L21/60

CPC classification number: H05K3/0094 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76877 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2021/60007 ,  H01L2224/16225 ,  H05K1/0201 ,  H05K1/115 ,  H05K3/4038

Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having thermally conductive vias in addition to electrically conductive vias. The thermally conductive vias help dissipate heat from one or more IC chips, through the glass interposer, into an organic carrying, and then, into an underlying substrate where it can be dissipated.

Abstract translation: 本发明一般涉及集成电路（IC）芯片封装，更具体地，涉及一种形成具有导电通孔的玻璃插入件以及导电通孔的结构和方法。 导热通孔有助于从一个或多个IC芯片（通过玻璃插入件）将热量散发到有机载体中，然后进入可以被耗散的底层基板。