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    Structures and SRAM bit cells integrating complementary field-effect transistors
    11.
    发明授权
    Structures and SRAM bit cells integrating complementary field-effect transistors 有权

    公开(公告)号：US11309319B2

    公开(公告)日：2022-04-19

    申请号：US16984468

    申请日：2020-08-04

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

    IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

    Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
    12.
    发明申请
    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS 有权

    公开(公告)号：US20220108950A1

    公开(公告)日：2022-04-07

    申请号：US17553924

    申请日：2021-12-17

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

    Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

    Fin-type field-effect transistors over one or more buried polycrystalline layers
    13.
    发明授权
    Fin-type field-effect transistors over one or more buried polycrystalline layers 有权

    公开(公告)号：US11164867B2

    公开(公告)日：2021-11-02

    申请号：US16534361

    申请日：2019-08-07

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Siva P. Adusumilli ,  Julien Frougier ,  Ruilong Xie ,  Anthony K. Stamper

    IPC: H01L29/04 ,  H01L29/786 ,  H01L27/088 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/324

    Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.

    NOVEL SPLIT GATE (SG) MEMORY DEVICE AND NOVEL METHODS OF MAKING THE SG-MEMORY DEVICE
    16.
    发明申请
    NOVEL SPLIT GATE (SG) MEMORY DEVICE AND NOVEL METHODS OF MAKING THE SG-MEMORY DEVICE 有权

    公开(公告)号：US20210151451A1

    公开(公告)日：2021-05-20

    申请号：US16683439

    申请日：2019-11-14

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Hui Zang ,  Ruilong Xie ,  Shesh Mani Pandey

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/423

    Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.

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