公开(公告)号：US11424377B2

公开(公告)日：2022-08-23

申请号：US17065862

申请日：2020-10-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Ramsey Hazbun

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/103 ,  H01L31/028

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

公开(公告)号：US11322639B2

公开(公告)日：2022-05-03

申请号：US16844606

申请日：2020-04-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Vibhor Jain ,  Ramsey Hazbun ,  Pernell Dongmo ,  Cameron E. Luce ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L31/107 ,  H01L31/18 ,  H01L31/028 ,  H01L31/0376

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.

公开(公告)号：US11296190B2

公开(公告)日：2022-04-05

申请号：US16743589

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L29/10 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/74

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.

公开(公告)号：US20220093744A1

公开(公告)日：2022-03-24

申请号：US17029667

申请日：2020-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Yves Ngu ,  Michael Zierak

IPC: H01L29/10 ,  H01L21/763 ,  H01L29/04 ,  H01L27/12

Abstract: Body-contacted semiconductor structures and methods of forming a body-contacted semiconductor structure. A semiconductor substrate, which contains of a single-crystal semiconductor material, includes a device region and a plurality of body contact regions each comprised of the single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are positioned between the polycrystalline layer and the device region, and the polycrystalline regions have a laterally-spaced arrangement with a gap between each adjacent pair of the polycrystalline regions. One of the plurality of body contact regions is arranged in the gap between each adjacent pair of the polycrystalline regions.

公开(公告)号：US11271077B2

公开(公告)日：2022-03-08

申请号：US16807453

申请日：2020-03-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  John J. Pekarik ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L27/01 ,  H01L21/76 ,  H01L29/06 ,  H01L29/04 ,  H01L21/762 ,  H01L27/102 ,  H01L29/737 ,  H01L27/12 ,  H01L21/324 ,  H01L29/32

Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.

公开(公告)号：US20210376159A1

公开(公告)日：2021-12-02

申请号：US16890063

申请日：2020-06-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Mark Levy ,  Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/763

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

公开(公告)号：US11163114B2

公开(公告)日：2021-11-02

申请号：US16549466

申请日：2019-08-23

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B1/00 ,  G02B6/122 ,  G02B6/125 ,  G02B6/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.

公开(公告)号：US11127816B2

公开(公告)日：2021-09-21

申请号：US16791214

申请日：2020-02-14

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Rajendran Krishnasamy ,  Steven M. Shank ,  Vibhor Jain

IPC: H01L29/08 ,  H01L29/49 ,  H01L29/16 ,  H01L29/737 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having one or more sealed airgap and methods of manufacture. The structure includes: a subcollector region in a substrate; a collector region above the substrate; a sealed airgap formed at least partly in the collector region; a base region adjacent to the collector region; and an emitter region adjacent to the base region.

公开(公告)号：US11063140B2

公开(公告)日：2021-07-13

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L27/082

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US20210111063A1

公开(公告)日：2021-04-15

申请号：US16598064

申请日：2019-10-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Ian McCallum-Cook ,  Michel J. Abou-Khalil

IPC: H01L21/763 ,  H01L29/06 ,  H01L23/66 ,  H01L21/265 ,  H01L21/324

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.