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72 条记录 (耗时 0.021 秒)

    Integrated chemical sensor for detecting odorous matters
    11.
    发明授权
    Integrated chemical sensor for detecting odorous matters 有权
    用于检测气味物质的集成化学传感器

    公开(公告)号：US08499613B2

    公开(公告)日：2013-08-06

    申请号：US13016086

    申请日：2011-01-28

    申请人： Federico Giovanni Ziglioli ,  Amedeo Maierna ,  Flavio Francesco Villa ,  Ubaldo Mastromatteo ,  Gabriele Barlocchi

    发明人： Federico Giovanni Ziglioli ,  Amedeo Maierna ,  Flavio Francesco Villa ,  Ubaldo Mastromatteo ,  Gabriele Barlocchi

    IPC分类号： G01N7/04

    CPC分类号： G01N33/0009

    摘要： A cartridge-like chemical sensor is formed by a housing having a base and a cover fixed to the base and provided with an input opening, an output hole and a channel for a gas to be analyzed. The channel extends in the cover between the input opening and the output hole and faces a printed circuit board carrying an integrated circuit having a sensitive region open toward the channel and of a material capable to bind with target chemicals in the gas to be analyzed. A fan is arranged in the housing, downstream of the integrated device, for sucking the gas after being analyzed, and is part of a thermal control system for the integrated circuit.

    摘要翻译： 盒式化学传感器由壳体形成，壳体具有固定到基座的基部和盖，并且设置有用于待分析气体的输入开口，输出孔和通道。 通道在输入开口和输出孔之间的盖中延伸，并且面向承载具有朝向通道开口的敏感区域的集成电路的印刷电路板和能够与要分析的气体中的目标化学物质结合的材料。 在集成装置的下游的壳体内设置风扇，用于在分析后吸入气体，并且是集成电路的热控制系统的一部分。

    CAPACITIVE SEMICONDUCTOR PRESSURE SENSOR
    12.
    发明申请
    CAPACITIVE SEMICONDUCTOR PRESSURE SENSOR 有权
    电容式半导体压力传感器

    公开(公告)号：US20120223402A1

    公开(公告)日：2012-09-06

    申请号：US13446976

    申请日：2012-04-13

    申请人： Flavio Francesco Villa ,  Gabriele Barlocchi ,  Pietro Corona ,  Benedetto Vigna ,  Lorenzo Baldo

    发明人： Flavio Francesco Villa ,  Gabriele Barlocchi ,  Pietro Corona ,  Benedetto Vigna ,  Lorenzo Baldo

    IPC分类号： H01L29/84

    CPC分类号： G01L9/0073 ,  G01L9/0045

    摘要： A capacitive semiconductor pressure sensor, comprising: a bulk region of semiconductor material; a buried cavity overlying a first part of the bulk region; and a membrane suspended above said buried cavity, wherein, said bulk region and said membrane are formed in a monolithic substrate, and in that said monolithic substrate carries structures for transducing the deflection of said membrane into electrical signals, wherein said bulk region and said membrane form electrodes of a capacitive sensing element, and said transducer structures comprise contact structures in electrical contact with said membrane and with said bulk region.

    摘要翻译： 一种电容半导体压力传感器，包括：半导体材料的主体区域; 覆盖大块区域的第一部分的掩埋腔; 以及悬浮在所述掩埋腔上方的膜，其中所述体积区域和所述膜形成在整体式衬底中，并且所述整体式衬底承载用于将所述膜的偏转转换成电信号的结构，其中所述体积区域和所述膜 形成电容感测元件的电极，并且所述换能器结构包括与所述膜电连接并与所述体积区域接触的接触结构。

    Method for forming horizontal buried channels or cavities in wafers of monocrystalline semiconductor material
    13.
    发明授权
    Method for forming horizontal buried channels or cavities in wafers of monocrystalline semiconductor material 有权
    在单晶半导体材料的晶片中形成水平埋入通道或空腔的方法

    公开(公告)号：US07705416B2

    公开(公告)日：2010-04-27

    申请号：US10667113

    申请日：2003-09-18

    申请人： Gabriele Barlocchi ,  Flavio Villa

    发明人： Gabriele Barlocchi ,  Flavio Villa

    IPC分类号： H01L29/00

    CPC分类号： H01L21/2007 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/76251 ,  H01L21/76262 ,  H01L21/764

    摘要： A method of forming buried cavities in a wafer of monocrystalline semiconductor material with at least one cavity formed in a substrate of monocrystalline semiconductor material by timed TMAH etching silicon; covering the cavity with a material inhibiting epitaxial growth; and growing a monocrystalline epitaxial layer above the substrate and the cavities. Thereby, the cavity is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane. The original wafer must have a plurality of elongate cavities or channels, parallel and adjacent to one another. Trenches are then excavated in the epitaxial layer as far as the channels, and the dividers between the channels are removed by timed TMAH etching.

    摘要翻译： 在单晶半导体材料的晶片中形成掩埋空穴的方法，其中至少一个腔通过定时的TMAH蚀刻硅在单晶半导体材料的衬底中形成; 用抑制外延生长的材料覆盖空腔; 以及在衬底和空腔上生长单晶外延层。 因此，腔体被单晶材料完全包围。 从该晶片开始，可以形成薄膜。 原始晶片必须具有彼此平行并相邻的多个细长空腔或通道。 然后在外延层中挖沟直到沟道，并且通过定时TMAH蚀刻去除沟道之间的分隔线。

    Process for manufacturing wafers of semiconductor material by layer transfer
    15.
    发明授权
    Process for manufacturing wafers of semiconductor material by layer transfer 有权
    通过层转移制造半导体材料的晶片的工艺

    公开(公告)号：US07348257B2

    公开(公告)日：2008-03-25

    申请号：US11225883

    申请日：2005-09-13

    申请人： Gabriele Barlocchi ,  Flavio Francesco Villa

    发明人： Gabriele Barlocchi ,  Flavio Francesco Villa

    IPC分类号： H01L21/30

    CPC分类号： H01L21/3247 ,  H01L21/3043 ,  H01L21/76251 ,  H01L21/76259

    摘要： A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.

    摘要翻译： 一种工艺使用半导体处理技术制造晶片。 在第一晶片的顶表面上形成接合层; 在属于第二晶片的半导体材料的衬底中挖出深沟槽。 半导体材料的顶层形成在衬底的顶部上，以封闭顶部的深沟槽并形成至少一个埋入空腔。 第二晶片的顶层通过结合层结合到第一晶片。 对这两个晶片进行热处理，其导致顶层的至少一部分与第一晶片的接合和掩埋腔的加宽。 以这种方式，将结合到第一晶片的顶层的部分与第二晶片的其余部分分离，以形成复合晶片。

    Process for manufacturing low-cost and high-quality SOI substrates
    17.
    发明授权
    Process for manufacturing low-cost and high-quality SOI substrates 有权

    公开(公告)号：US07071073B2

    公开(公告)日：2006-07-04

    申请号：US10331189

    申请日：2002-12-26

    申请人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    发明人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76262 ,  H01L21/31662 ,  H01L21/76208

    摘要： For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.

    Process for manufacturing a SOI wafer with buried oxide regions without cusps
    20.
    发明授权
    Process for manufacturing a SOI wafer with buried oxide regions without cusps 失效
    用于制造具有埋藏氧化物区域的SOI晶片的方法，而不具有尖端

    公开(公告)号：US06362070B1

    公开(公告)日：2002-03-26

    申请号：US09558934

    申请日：2000-04-26

    申请人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    发明人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    IPC分类号： H01L2176

    CPC分类号： H01L21/02238 ,  H01L21/02299 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76208 ,  H01L21/76248

    摘要： A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth. The masking regions and the retarding regions are formed through two successive implants, including an angle implant, wherein the protruding regions shield the bottom portions of the adjacent protruding regions, as well as the bottom of the trenches, and a vertical implant is made perpendicularly to the wafer.

    摘要翻译： 一种用于制造具有埋藏氧化物区域而没有尖端的SOI晶片的方法，包括在单晶半导体材料的晶片中形成在横向延伸并限定突出区域的沟槽; 形成掩蔽区域，注入氮离子，掩蔽区域完全围绕突出区域的尖端; 以及在沟槽的底部形成延迟区域，其中以比掩蔽区域低的剂量注入氮。 然后进行热氧化，并从突出区域的底部开始，然后向下移动; 由此，形成了埋入氧化物的连续区域，并且由对应于突出区域的尖端的非氧化区域覆盖并形成用于随后的外延生长的核区域。 掩模区域和延迟区域通过两个连续的植入物形成，包括角度注入，其中突出区域屏蔽相邻突出区域的底部以及沟槽的底部，垂直植入物垂直于 晶圆。