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11.发明申请INTEGRATED CIRCUIT WITH BUILT-IN HEATING CIRCUITRY TO REVERSE OPERATIONAL DEGENERATION 审中-公开具有内置加热电路的集成电路反向运行变化公开(公告)号：US20100025811A1
公开(公告)日：2010-02-04
申请号：US12516499
申请日：2007-11-29
IPC分类号： H01L23/34
CPC分类号： H01L27/105 , H01L21/67103 , H01L23/345 , H01L27/11517 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).
摘要翻译： 集成电路装置（100）包括结构（104），其显示作为使用功能的性能劣化（例如，闪存单元的隧穿氧化物内的累积缺陷或电荷存储层内的俘获电荷）和加热电路（101 ）设置在结构附近，以将结构加热到降低退化的温度。 存储器件的字线或位线用作加热元件（107）。
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公开(公告)号：US20080102569A1
公开(公告)日：2008-05-01
申请号：US12002828
申请日：2007-12-19
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译： 提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域 的沟渠 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。
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13.发明授权Modified gate processing for optimized definition of array and logic devices on same chip 失效改进的门处理，用于在同一芯片上优化阵列和逻辑器件的定义公开(公告)号：US06403423B1
公开(公告)日：2002-06-11
申请号：US09713272
申请日：2000-11-15
申请人： Mary E. Weybright , Gary Bronner , Richard A. Conti , Ramachandra Divakaruni , Jeffrey Peter Gambino , Peter Hoh , Uwe Schroeder
发明人： Mary E. Weybright , Gary Bronner , Richard A. Conti , Ramachandra Divakaruni , Jeffrey Peter Gambino , Peter Hoh , Uwe Schroeder
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L21/76897 , H01L21/823456 , H01L27/1052 , H01L27/10873
摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.
摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些电介质间隔物允许阵列栅极导体抗蚀剂线被制成 - 小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。
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14.发明授权Spacers to block deep junction implants and silicide formation in integrated circuits 失效在集成电路中阻挡深结植入物和硅化物形成的间隔物公开(公告)号：US06174756B1
公开(公告)日：2001-01-16
申请号：US08940236
申请日：1997-09-30
IPC分类号： H01L2100
CPC分类号： H01L27/10844 , H01L21/823418
摘要： An efficient method of forming deep junction implants in one region without affecting the implant of a second region of an integrated circuit is provided. This is achieved by forming spacers of deep junction devices with the same material used to fill the gaps of shallow junction devices.
摘要翻译： 提供了在一个区域内形成深结植入物而不影响集成电路的第二区域的植入的有效方法。 这通过用与填充浅结设备的间隙的相同材料形成深接合器件的间隔件来实现。
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15.发明授权Methods and circuits for detecting and reporting high-energy particles using mobile phones and other portable computing devices 有权使用移动电话和其他便携式计算设备检测和报告高能粒子的方法和电路公开(公告)号：US08583071B2
公开(公告)日：2013-11-12
申请号：US13144683
申请日：2009-12-18
申请人： Scott Best , Gary Bronner , Ely Tsern
发明人： Scott Best , Gary Bronner , Ely Tsern
CPC分类号： H04W36/385 , G01T7/00 , H04M2250/12
摘要： Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters.
摘要翻译： 描述的是携带使用常用半导体存储器形成的辐射探测器的移动电话。 辐射探测器对常规电话中可用的几乎没有额外的硬件，因此可以以少量的费用或包装修改来集成。 低成本支持检测器的广泛分布。 从装有探测器的手机的星座收集的数据可用于定位错误或被盗的核材料或其他潜在危险的辐射源。 电话用户可以收到附近的辐射危险警报，并且聚合的手机特定的错误数据可以用作用户特定的剂量计。
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16.发明申请Methods and Circuits for Detecting and Reporting High-Energy Particles Using Mobile Phones and Other Portable Computing Devices 有权使用手机和其他便携式计算设备检测和报告高能粒子的方法和电路公开(公告)号：US20110275356A1
公开(公告)日：2011-11-10
申请号：US13144683
申请日：2009-12-18
申请人： Scott Best , Gary Bronner , Ely Tsem
发明人： Scott Best , Gary Bronner , Ely Tsem
CPC分类号： H04W36/385 , G01T7/00 , H04M2250/12
摘要： Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters.
摘要翻译： 描述的是携带使用常用半导体存储器形成的辐射探测器的移动电话。 辐射探测器对常规电话中可用的几乎没有额外的硬件，因此可以以少量的费用或包装修改来集成。 低成本支持检测器的广泛分布。 从装有探测器的手机的星座收集的数据可用于定位错误或被盗的核材料或其他潜在危险的辐射源。 电话用户可以收到附近的辐射危险警报，并且聚合的手机特定的错误数据可以用作用户特定的剂量计。
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公开(公告)号：US20060175660A1
公开(公告)日：2006-08-10
申请号：US10906238
申请日：2005-02-10
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译： 提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。
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公开(公告)号：US20050247966A1
公开(公告)日：2005-11-10
申请号：US10709450
申请日：2004-05-06
IPC分类号： H01L21/8242 , H01L27/108 , H01L31/119
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译： 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。
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公开(公告)号：US20070249133A1
公开(公告)日：2007-10-25
申请号：US11308604
申请日：2006-04-11
申请人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
发明人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译： 一种在半导体器件上形成导电间隔物的方法。 该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层 。 任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。
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公开(公告)号：US20060091442A1
公开(公告)日：2006-05-04
申请号：US11298800
申请日：2005-12-09
IPC分类号： H01L29/94
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
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