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    Capacitance evaluation apparatuses and methods
    12.
    发明授权
    Capacitance evaluation apparatuses and methods 有权
    电容评估装置及方法

    公开(公告)号：US09267980B2

    公开(公告)日：2016-02-23

    申请号：US13210264

    申请日：2011-08-15

    申请人： Xinwei Guo ,  James I. Esteves ,  Arvind Muralidharan ,  Nicholas Hendrickson

    发明人： Xinwei Guo ,  James I. Esteves ,  Arvind Muralidharan ,  Nicholas Hendrickson

    IPC分类号： G01R31/12 ,  G01R31/08 ,  G01R31/02 ,  G11C29/02 ,  G11C29/50

    CPC分类号： G01R31/028 ,  G01R31/024 ,  G01R31/025 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50016 ,  G11C2029/5006

    摘要： Apparatus and methods for evaluating leakage currents of capacitances are described. Capacitances having excessive leakage currents may be disabled from use. An example apparatus includes a leakage detection circuit configured to be coupled to a capacitance block. The leakage detection circuit is configured to determine whether a leakage current of a capacitance of the capacitance block exceeds a current limit and is further configured to provide an output indicative of a status of the capacitance. A detection controller is coupled to the leakage detection circuit and a register, and the detection controller is configured to store data in the register indicative of the status of the capacitance based at least in part on the signal from the leakage detection circuit.

    摘要翻译： 描述用于评估电容的漏电流的装置和方法。 具有过大漏电流的电容可能会被禁止使用。 示例性装置包括被配置为耦合到电容块的泄漏检测电路。 泄漏检测电路被配置为确定电容块的电容的漏电流是否超过电流限制，并且还被配置为提供指示电容状态的输出。 检测控制器耦合到泄漏检测电路和寄存器，并且检测控制器被配置为至少部分地基于来自泄漏检测电路的信号将数据存储在指示电容状态的寄存器中。

    Memories and methods for performing column repair
    13.
    发明授权
    Memories and methods for performing column repair 有权
    用于执行色谱柱修复的记忆和方法

    公开(公告)号：US09043661B2

    公开(公告)日：2015-05-26

    申请号：US13483407

    申请日：2012-05-30

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： G11C29/00 ,  G01R31/28 ,  G06F11/00 ,  G11C7/00 ,  G11C11/34

    CPC分类号： G11C29/70 ,  G06F11/1048 ,  G11C16/08 ,  G11C16/14 ,  G11C16/28 ,  G11C29/806 ,  G11C29/82

    摘要： Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.

    摘要翻译： 适于在编程操作期间修复单个不可编程单元的存储器件，以及在随后的擦除操作期间修复包含不可编程单元的列。 这样的存储器件的编程包括确定单个单元不可编程并修复单个单元，以及响应于随后的擦除操作修复包含单个单元的列。

    Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory
    14.
    发明授权
    Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory 有权
    块行解码器，存储器块行解码器，存储器，用于取消存储器解码器的方法和选择存储器块的方法

    公开(公告)号：US08625382B2

    公开(公告)日：2014-01-07

    申请号：US13168699

    申请日：2011-06-24

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/12

    摘要： Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured to bias a block select switch of the decoder switch tree with a first voltage while the block-row decoder is deselected and further configured to bias decoders switches of the decoder switch tree that are coupled to the block select switch with a second voltage while the block-row decoder is deselected, the second voltage less than the first voltage. An example method of deselecting a decoder of a memory includes providing decoder signals having different voltages to decoder switches from at least two different levels of a decoder switch tree while the decoder is deselected.

    摘要翻译： 公开了块行解码器，存储器块行解码器，存储器，用于取消存储器解码器的方法和选择存储器块的方法。 示例性存储器块行解码器包括多个块行解码器，每个块行解码器具有解码器开关树。 每个块行解码器被配置为在块排解码器被取消选择时以第一电压偏置解码器开关树的块选择开关，并且还被配置为偏置解码器开关树的解码器开关，耦合到块选择开关 在块排解码器被取消选择时具有第二电压，第二电压小于第一电压。 取消选择存储器的解码器的示例方法包括：在解码器被取消选择的同时，从解码器开关树的至少两个不同级别提供具有不同电压的解码器信号到解码器开关。

    DETERMINING AND TRANSFERRING DATA FROM A MEMORY ARRAY
    15.
    发明申请
    DETERMINING AND TRANSFERRING DATA FROM A MEMORY ARRAY 有权
    从存储阵列确定和传输数据

    公开(公告)号：US20130028017A1

    公开(公告)日：2013-01-31

    申请号：US13191836

    申请日：2011-07-27

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： G11C16/26 ,  G11C16/04

    CPC分类号： G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

    摘要： Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.

    摘要翻译： 公开了操作存储器件的装置和方法。 在一种这样的方法中，存储器单元的数据状态的第一部分被确定并从存储器件传送，同时继续确定相同存储器单元的数据状态的剩余部分。 在至少一种方法中，在第一感测阶段期间确定存储器单元的数据状态，并且在存储器单元经历额外的检测相位时传送，以确定存储器单元的数据状态的附加部分。

    Compensated comparator for use in lower voltage, higher speed non-volatile memory
    18.
    发明授权
    Compensated comparator for use in lower voltage, higher speed non-volatile memory 失效
    补偿比较器用于低电压，高速度非易失性存储器

    公开(公告)号：US07498850B2

    公开(公告)日：2009-03-03

    申请号：US11767227

    申请日：2007-06-22

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： H03K5/22

    CPC分类号： H03K5/22

    摘要： Briefly, in accordance with one or more embodiments, an offset compensated comparator is capable of being utilized for higher speed, lower voltage use. The comparator comprises a cross-coupled latch comprising n type devices and p type devices. The threshold mismatch between n type devices is captured on capacitors coupled to the gates of the n type devices to capture the mismatch between the devices. After the threshold mismatch is captured, the comparator can be used as a typical cross coupled latch.

    摘要翻译： 简而言之，根据一个或多个实施例，偏移补偿比较器能够用于更高速度，更低电压的使用。 该比较器包括一个交叉耦合的锁存器，其包括n型装置和p型装置。 n型器件之间的阈值失配在与n型器件的栅极耦合的电容器上捕获，以捕获器件之间的失配。 在捕获阈值失配之后，比较器可以用作典型的交叉耦合锁存器。

    COMPENSATED COMPARATOR FOR USE IN LOWER VOLTAGE, HIGHER SPEED NON-VOLATILE MEMORY
    19.
    发明申请
    COMPENSATED COMPARATOR FOR USE IN LOWER VOLTAGE, HIGHER SPEED NON-VOLATILE MEMORY 失效
    用于低电压，高速非易失性存储器的补偿比较器

    公开(公告)号：US20080315922A1

    公开(公告)日：2008-12-25

    申请号：US11767227

    申请日：2007-06-22

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： H03K5/22

    CPC分类号： H03K5/22

    摘要： Briefly, in accordance with one or more embodiments, an offset compensated comparator is capable of being utilized for higher speed, lower voltage use. The comparator comprises a cross-coupled latch comprising n type devices and p type devices. The threshold mismatch between n type devices is captured on capacitors coupled to the gates of the n type devices to capture the mismatch between the devices. After the threshold mismatch is captured, the comparator can be used as a typical cross coupled latch.

    摘要翻译： 简而言之，根据一个或多个实施例，偏移补偿比较器能够用于更高速度，更低电压的使用。 该比较器包括一个交叉耦合的锁存器，其包括n型装置和p型装置。 n型器件之间的阈值失配在与n型器件的栅极耦合的电容器上捕获，以捕获器件之间的失配。 在捕获阈值失配之后，比较器可以用作典型的交叉耦合锁存器。