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21 条记录 (耗时 0.011 秒)

    COMPLEMENTARY DECODING FOR NON-VOLATILE MEMORY
    1.
    发明申请
    COMPLEMENTARY DECODING FOR NON-VOLATILE MEMORY 有权
    非易失性存储器的补充解码

    公开(公告)号：US20140078821A1

    公开(公告)日：2014-03-20

    申请号：US13616545

    申请日：2012-09-14

    申请人： Nicholas HENDRICKSON

    发明人： Nicholas HENDRICKSON

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C8/10 ,  G11C7/00 ,  G11C11/00 ,  G11C11/4087 ,  G11C11/4091 ,  G11C13/0026 ,  G11C16/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

    摘要： Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular memory device operations are performed.

    摘要翻译： 公开了存储器件中的解码和解码器电路。 当存储器件中执行存储器件操作时，阵列线偏置或浮动。 在至少一个实施例中，解码器电路包括用于在执行特定存储器件操作时将阵列线或浮动阵列线偏置在存储器件中的互补器件。

    MEMORIES AND METHODS FOR PERFORMING COLUMN REPAIR
    2.
    发明申请
    MEMORIES AND METHODS FOR PERFORMING COLUMN REPAIR 有权
    用于执行柱修复的记忆和方法

    公开(公告)号：US20130326292A1

    公开(公告)日：2013-12-05

    申请号：US13483407

    申请日：2012-05-30

    申请人： Nicholas HENDRICKSON

    发明人： Nicholas HENDRICKSON

    IPC分类号： G11C29/00

    CPC分类号： G11C29/70 ,  G06F11/1048 ,  G11C16/08 ,  G11C16/14 ,  G11C16/28 ,  G11C29/806 ,  G11C29/82

    摘要： Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.

    摘要翻译： 适于在编程操作期间修复单个不可编程单元的存储器件，以及在随后的擦除操作期间修复包含不可编程单元的列。 这样的存储器件的编程包括确定单个单元不可编程并修复单个单元，以及响应于随后的擦除操作修复包含单个单元的列。

    SIGNAL MANAGEMENT IN A MEMORY DEVICE
    3.
    发明申请
    SIGNAL MANAGEMENT IN A MEMORY DEVICE 有权
    内存设备中的信号管理

    公开(公告)号：US20130272073A1

    公开(公告)日：2013-10-17

    申请号：US13443913

    申请日：2012-04-11

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C16/06 ,  G11C7/10 ,  G11C7/109 ,  G11C7/22 ,  G11C8/06

    摘要： Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating characteristics within a memory device. In at least one embodiment, a command signal management circuit is configured to selectively block a command signal while a memory device operation is being performed. In at least one other embodiment, one or more command blocking circuits are configured to selectively pass and block one or more command signals generated by a memory access device coupled to the memory device while a memory device operation is being performed in the memory device.

    摘要翻译： 公开了存储器装置中的命令信号管理方法和电路。 选择性地传递和阻止命令信号以在存储器件内实现安全的操作特性。 在至少一个实施例中，命令信号管理电路被配置为在正在执行存储器件操作的同时选择性地阻止命令信号。 在至少另一个实施例中，一个或多个命令阻塞电路被配置为在存储器件中正在执行存储器件操作时选择性地传递和阻止由耦合到存储器件的存储器访问器件产生的一个或多个命令信号。

    BLOCK-ROW DECODERS, MEMORY BLOCK-ROW DECODERS, MEMORIES, METHODS FOR DESELECTING A DECODER OF A MEMORY AND METHODS OF SELECTING A BLOCK OF MEMORY
    4.
    发明申请
    BLOCK-ROW DECODERS, MEMORY BLOCK-ROW DECODERS, MEMORIES, METHODS FOR DESELECTING A DECODER OF A MEMORY AND METHODS OF SELECTING A BLOCK OF MEMORY 有权
    块式解码器，存储器块解码器，存储器，用于描述存储器的解码器的方法和选择存储器块的方法

    公开(公告)号：US20120327735A1

    公开(公告)日：2012-12-27

    申请号：US13168699

    申请日：2011-06-24

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： G11C8/10 ,  G11C8/00

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/12

    摘要： Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured to bias a block select switch of the decoder switch tree with a first voltage while the block-row decoder is deselected and further configured to bias decoders switches of the decoder switch tree that are coupled to the block select switch with a second voltage while the block-row decoder is deselected, the second voltage less than the first voltage. An example method of deselecting a decoder of a memory includes providing decoder signals having different voltages to decoder switches from at least two different levels of a decoder switch tree while the decoder is deselected.

    摘要翻译： 公开了块行解码器，存储器块行解码器，存储器，用于取消存储器解码器的方法和选择存储器块的方法。 示例性存储器块行解码器包括多个块行解码器，每个块行解码器具有解码器开关树。 每个块行解码器被配置为在块排解码器被取消选择的同时以第一电压偏置解码器开关树的块选择开关，并且还被配置为偏置解码器开关树的解码器开关，其耦合到块选择开关 在块排解码器被取消选择时具有第二电压，第二电压小于第一电压。 取消选择存储器的解码器的示例方法包括：在解码器被取消选择的同时，从解码器开关树的至少两个不同级别提供具有不同电压的解码器信号到解码器开关。

    Detection and correction of defects in semiconductor memories
    5.
    发明授权
    Detection and correction of defects in semiconductor memories 有权
    检测和校正半导体存储器中的缺陷

    公开(公告)号：US07639535B2

    公开(公告)日：2009-12-29

    申请号：US11601124

    申请日：2006-11-17

    申请人： Nicholas Hendrickson ,  Gerald Barkley

    发明人： Nicholas Hendrickson ,  Gerald Barkley

    IPC分类号： G11C11/34

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/4401 ,  G11C29/70 ,  G11C2029/4002 ,  G11C2029/5006

    摘要： A non-volatile memory may have memory portions, such as blocks or other granularities of units of memory, which may fail in actual use. These defective portions can be replaced with other portions which may, in some cases, be of corresponding size. In some embodiments, defects may be detected using a current sensor which detects the current drawn in actual operation. If an excessive current is drawn, this may be detected, the defective unit deactivated, and a replacement provided in its stead. This may result in the repair of a defect with little inconvenience to the user in some embodiments.

    摘要翻译： 非易失性存储器可以具有诸如块或存储器单位的其他粒度的存储器部分，其可能在实际使用中失败。 这些缺陷部分可以用其他部分替代，在某些情况下，这些部分可能具有相应的尺寸。 在一些实施例中，可以使用检测在实际操作中绘制的电流的电流传感器来检测缺陷。 如果画出过大的电流，则可能会检测到这种情况，故障单元会被停用，并且替换为替代。 这在一些实施例中可能导致对用户的少量不便的修复。

    Signal management in a memory device
    6.
    发明授权
    Signal management in a memory device 有权
    存储设备中的信号管理

    公开(公告)号：US09159383B2

    公开(公告)日：2015-10-13

    申请号：US13443913

    申请日：2012-04-11

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/06

    CPC分类号： G11C16/06 ,  G11C7/10 ,  G11C7/109 ,  G11C7/22 ,  G11C8/06

    摘要： Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating characteristics within a memory device. In at least one embodiment, a command signal management circuit is configured to selectively block a command signal while a memory device operation is being performed. In at least one other embodiment, one or more command blocking circuits are configured to selectively pass and block one or more command signals generated by a memory access device coupled to the memory device while a memory device operation is being performed in the memory device.

    摘要翻译： 公开了存储器装置中的命令信号管理方法和电路。 选择性地传递和阻止命令信号以在存储器件内实现安全的操作特性。 在至少一个实施例中，命令信号管理电路被配置为在正在执行存储器件操作的同时选择性地阻止命令信号。 在至少另一个实施例中，一个或多个命令阻塞电路被配置为在存储器件中正在执行存储器件操作时选择性地传递和阻止由耦合到存储器件的存储器访问器件产生的一个或多个命令信号。

    Determining and transferring data from a memory array
    8.
    发明授权
    Determining and transferring data from a memory array 有权
    从存储器阵列确定和传输数据

    公开(公告)号：US08625345B2

    公开(公告)日：2014-01-07

    申请号：US13191836

    申请日：2011-07-27

    申请人： Nicholas Hendrickson

    发明人： Nicholas Hendrickson

    IPC分类号： G11C16/26

    CPC分类号： G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

    摘要： Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.

    摘要翻译： 公开了操作存储器件的装置和方法。 在一种这样的方法中，存储器单元的数据状态的第一部分被确定并从存储器件传送，同时继续确定相同存储器单元的数据状态的剩余部分。 在至少一种方法中，在第一感测阶段期间确定存储器单元的数据状态，并且在存储器单元经历额外的检测相位时传送，以确定存储器单元的数据状态的附加部分。

    Detection and correction of defects in semiconductor memories
    10.
    发明申请
    Detection and correction of defects in semiconductor memories 有权
    检测和校正半导体存储器中的缺陷

    公开(公告)号：US20080117681A1

    公开(公告)日：2008-05-22

    申请号：US11601124

    申请日：2006-11-17

    申请人： Nicholas Hendrickson ,  Gerald Barkley

    发明人： Nicholas Hendrickson ,  Gerald Barkley

    IPC分类号： G11C16/06 ,  G11C29/00

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/4401 ,  G11C29/70 ,  G11C2029/4002 ,  G11C2029/5006

    摘要： A non-volatile memory may have memory portions, such as blocks or other granularities of units of memory, which may fail in actual use. These defective portions can be replaced with other portions which may, in some cases, be of corresponding size. In some embodiments, defects may be detected using a current sensor which detects the current drawn in actual operation. If an excessive current is drawn, this may be detected, the defective unit deactivated, and a replacement provided in its stead. This may result in the repair of a defect with little inconvenience to the user in some embodiments.

    摘要翻译： 非易失性存储器可以具有诸如块或存储器单位的其他粒度的存储器部分，其可能在实际使用中失败。 这些缺陷部分可以用其他部分替代，在某些情况下，这些部分可能具有相应的尺寸。 在一些实施例中，可以使用检测在实际操作中绘制的电流的电流传感器来检测缺陷。 如果画出过大的电流，则可能会检测到这种情况，故障单元会被停用，并且替换为替代。 这在一些实施例中可能导致对用户的少量不便的修复。