公开(公告)号：US11362177B2

公开(公告)日：2022-06-14

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.

公开(公告)号：US11205699B2

公开(公告)日：2021-12-21

申请号：US16655429

申请日：2019-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Julien Frougier ,  Ali Razavieh

IPC: H01L29/08 ,  H01L29/78

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.

公开(公告)号：US11094822B1

公开(公告)日：2021-08-17

申请号：US16751380

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Judson R. Holt ,  Shiv Kumar Mishra

IPC: H01L29/76 ,  H01L21/84 ,  H01L29/80 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

公开(公告)号：US11916136B2

公开(公告)日：2024-02-27

申请号：US17739092

申请日：2022-05-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander Derrickson ,  Judson Holt

IPC: H01L29/73 ,  H01L29/735 ,  H01L21/265 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6625

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer on a semiconductor substrate, a second terminal having a second raised semiconductor layer on the semiconductor substrate, and an intrinsic base on the semiconductor substrate. The intrinsic base is positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The intrinsic base includes a portion containing silicon-germanium with a germanium concentration that is graded in the lateral direction.

公开(公告)号：US20230275083A1

公开(公告)日：2023-08-31

申请号：US17807899

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson

IPC: H01L27/06 ,  H01L29/735 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8249 ,  H01L29/66

CPC classification number: H01L27/0623 ,  H01L29/735 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/8249 ,  H01L29/6625 ,  H01L29/66742 ,  H01L29/66439

Abstract: Disclosed are a forksheet semiconductor structure and a method of forming the structure. The structure can include a dielectric body with a first sidewall and a second sidewall opposite the first sidewall. The structure can include a first transistor, which incorporates first semiconductor nanosheet(s) positioned laterally immediately adjacent to the first sidewall of the dielectric body, and a second transistor, which incorporates second semiconductor nanosheet(s) positioned laterally immediately adjacent to the second sidewall. The first transistor and the second transistor can both be bipolar junction transistors (BJTs) (e.g., PNP-type BJTs, NPN-type BJTs or a PNP-type BJT and an NPN-type BJT). Alternatively, the first transistor can be a BJT (e.g., a PNP-type BJT or an NPN-type BJT) and the second transistor can be a field effect transistor (FET) (e.g., an N-type FET (NFET) or a P-type FET (PFET)).

公开(公告)号：US11646361B2

公开(公告)日：2023-05-09

申请号：US17191886

申请日：2021-03-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Haiting Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/7851

Abstract: A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed.

公开(公告)号：US20220199810A1

公开(公告)日：2022-06-23

申请号：US17130121

申请日：2020-12-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Ali Razavieh ,  Haiting Wang

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

公开(公告)号：US20210234045A1

公开(公告)日：2021-07-29

申请号：US16751380

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S, Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Judson R. Holt ,  Shiv Kumar Mishra

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

公开(公告)号：US20210233999A1

公开(公告)日：2021-07-29

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.