-
公开(公告)号：US10153729B2
公开(公告)日：2018-12-11
申请号：US15141410
申请日：2016-04-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Suhas Kumar , John Paul Strachan , Gary Gibson , R. Stanley Williams
Abstract: In some examples, a device includes a nano-scale oscillator that exhibits chaotic oscillation responsive to a control input to the nano-scale oscillator, where the control input including a tunable input parameter.
-
公开(公告)号：US10109346B2
公开(公告)日：2018-10-23
申请号：US15320788
申请日：2014-07-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Hans S. Cho , Gary Gibson , Brent Buchanan
Abstract: According to an example, an apparatus may include an input line, an output line, and a memory cell connected between the input line and the output line. The memory cell may include a memristor connected in series with a selector. The apparatus may also include a shunt device connected to the input line, in which the shunt device is to divert a portion of current away from the memory cell in response to a voltage at the input line being greater than a threshold voltage.
-
公开(公告)号：US09905757B2
公开(公告)日：2018-02-27
申请号：US15032913
申请日：2013-11-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Byungjoon Choi , Jianhua Yang , R. Stanley Williams , Gary Gibson , Warren Jackson
CPC classification number: H01L45/1226 , H01L27/2418 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A nonlinear memristor device with a three-layer selector includes a memristor in electrical series with a three-layer selector. The memristor comprises at least one electrically conducting layer and at least one electrically insulating layer. The three-layer selector comprises a three-layer structure selected from the group consisting of XN—XO—XN; XN—YO—ZN; XN—YO—XN; XO—XN—XO; XO—YN—XO; XO—YN—ZO; XO—YO—XO; XO—YO—ZO; XN—YN—ZN; and XN—YN—XN, X represents a compound-forming metal different from Y and Z.
-
公开(公告)号：US20180006088A1
公开(公告)日：2018-01-04
申请号：US15539929
申请日：2015-01-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Xia Sheng , Kyung Min , Gary Gibson
CPC classification number: H01L27/2463 , H01L27/2409 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266
Abstract: One example includes a resistive random access memory (ReRAM) device. The device includes a set of electrodes to receive a voltage. The device also includes a memristor element to at least one of store and readout a memory state in response to a current that flows through the ReRAM device in response to the voltage. The device further includes a selector element having a dynamic current-density area with respect to the voltage.
-
公开(公告)号：US09812500B2
公开(公告)日：2017-11-07
申请号：US15114010
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Gary Gibson , Warren Jackson , R. Stanley Williams
CPC classification number: H01L27/2418 , G11C7/04 , G11C11/1659 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/73 , G11C2213/76 , H01L45/00 , H01L45/1286 , H01L45/145
Abstract: A circuit component that exhibits a region of negative differential resistance includes: a first layer of material; and a second layer of material in contact with the first layer of material, the contact forming a first self-heating interface. The first self-heating interface is structured such that an electrical current flowing from the first layer of material to the second layer of material encounters an electrical impedance occurring at the first interface that is greater than any electrical impedance occurring in the first and second layers of material, wherein heating occurring at the first interface is dominated by Joule heating caused by the electrical impedance occurring at the first interface, and wherein the electrical impedance occurring at the first interface decreases with increasing temperature to induce a region of negative differential resistance.
-
Patent Agency Ranking
公开(公告)号：US20170271406A1
公开(公告)日：2017-09-21
申请号：US15500053
申请日：2015-02-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jianhua Yang , Gary Gibson , Zhiyong Li
CPC classification number: H01L27/2409 , H01L45/04 , H01L45/146
Abstract: A superlinear selector includes a first electrode, a second electrode, and an active layer coupled in series between the first electrode and the second electrode. The active layer includes a superlinear electrical conductor and an electrical insulator. One of the superlinear electrical conductor and the electrical insulator forms a matrix in which the other of the superlinear electrical conductor and the electrical insulator is dispersed.
-
公开(公告)号：US09747976B2
公开(公告)日：2017-08-29
申请号：US15112748
申请日：2014-01-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Warren Jackson , Gary Gibson
CPC classification number: G11C13/0002 , G11C16/0466 , H01L45/10 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146
Abstract: A charge trapping memristor is disclosed. An example charge trapping memristor includes a first electrode and second electrode configured on opposite sides of a channel to generate an electric potential across the channel, and a charge barrier. The example charge trapping memristor also includes a charge trapping material configured to store and release an electric charge therein, wherein storing and releasing the electric charge changes electrical properties of the channel.
-
公开(公告)号：US09721656B2
公开(公告)日：2017-08-01
申请号：US15113908
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Gregg B. Lesartre , Gary Gibson , Erik Ordentlich , Yoocharn Jeon
CPC classification number: G11C13/003 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/77 , H01L27/2463
Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.
-
公开(公告)号：US20170200495A1
公开(公告)日：2017-07-13
申请号：US15320788
申请日：2014-07-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Hans S. Cho , Gary Gibson , Brent Buchanan
CPC classification number: G11C13/004 , G11C7/04 , G11C13/0007 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C2213/72 , G11C2213/76 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146
Abstract: According to an example, an apparatus may include an input line, an output line, and a memory cell connected between the input line and the output line. The memory cell may include a memristor connected in series with a selector. The apparatus may also include a shunt device connected to the input line, in which the shunt device is to divert a portion of current away from the memory cell in response to a voltage at the input line being greater than a threshold voltage.
-
公开(公告)号：US20160343430A1
公开(公告)日：2016-11-24
申请号：US15112748
申请日：2014-01-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Warren Jackson , Gary Gibson
CPC classification number: G11C13/0002 , G11C16/0466 , H01L45/10 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146
Abstract: A charge trapping memristor is disclosed. An example charge trapping memristor includes a first electrode and second electrode configured on opposite sides of a channel to generate an electric potential across the channel, and a charge barrier. The example charge trapping memristor also includes a charge trapping material configured to store and release an electric charge therein, wherein storing and releasing the electric charge changes electrical properties of the channel.
Abstract translation: 公开了一种电荷捕获忆阻器。 示例性电荷俘获忆阻器包括配置在通道的相对侧上的第一电极和第二电极，以在通道上产生电位和电荷屏障。 示例性电荷俘获忆阻器还包括构造成在其中存储和释放电荷的电荷捕获材料，其中存储和释放电荷改变通道的电特性。
-
-
-
-
-
-
-
-
-
Search Results
28
records
(took 0.03 seconds)
