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    Semiconductor devices having a field effect transistor and methods of fabricating the same
    11.
    发明授权
    Semiconductor devices having a field effect transistor and methods of fabricating the same 有权
    具有场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US07247896B2

    公开(公告)日：2007-07-24

    申请号：US11090740

    申请日：2005-03-24

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78687 ,  Y10S438/933

    摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

    摘要翻译： 提供具有场效应晶体管的半导体器件及其形成方法。 半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。 栅电极优选地跨过器件有源图案，由栅极绝缘层插入。 支撑图案优选地插入在器件活性图案和基底之间。 支撑图案可以设置在栅电极下方。 填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。 填充绝缘图案可以设置在源极/漏极区域下方。 栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。

    NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS
    12.
    发明申请
    NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS 有权
    非挥发性半导体器件，包括浮动门和相关系统

    公开(公告)号：US20110156125A1

    公开(公告)日：2011-06-30

    申请号：US13040380

    申请日：2011-03-04

    申请人： Se-Hoon LEE ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

    发明人： Se-Hoon LEE ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

    摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

    摘要翻译： 存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅 浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

    Semiconductor device employing buried insulating layer and method of fabricating the same
    14.
    发明授权
    Semiconductor device employing buried insulating layer and method of fabricating the same 失效
    采用埋层绝缘层的半导体器件及其制造方法

    公开(公告)号：US07575964B2

    公开(公告)日：2009-08-18

    申请号：US11944260

    申请日：2007-11-21

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    IPC分类号： H01L21/337

    CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

    摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

    摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

    Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces
    16.
    发明授权
    Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces 有权
    使用牺牲层和空隙空间制造绝缘体上半导体（SOI）衬底和半导体器件的方法

    公开(公告)号：US07265031B2

    公开(公告)日：2007-09-04

    申请号：US10972972

    申请日：2004-10-25

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

    摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

    摘要翻译： 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

    Double gate MOS transistors
    18.
    发明授权
    Double gate MOS transistors 失效
    双栅MOS晶体管

    公开(公告)号：US06940129B2

    公开(公告)日：2005-09-06

    申请号：US10715664

    申请日：2003-11-18

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654

    摘要： A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode. The top gate electrode overlaps with the bottom gate electrode and is insulated from the transistor active region. Methods of fabricating such transistors are also provided.

    摘要翻译： 双栅MOS晶体管包括限定在半导体衬底中的衬底有源区和位于衬底有源区上方并与衬底有源区重叠的晶体管有源区。 至少一个半导体柱穿透晶体管有源区并与衬底有源区接触。 半导体柱支撑晶体管有源区，使得晶体管有源区与衬底有源区间隔开。 至少一个底栅电极填充晶体管有源区和衬底有源区之间的空间。 底栅电极与衬底有源区，晶体管有源区和半导体柱绝缘。 至少一个顶栅电极跨越晶体管有源区，并且具有与底栅电极的侧壁接触的至少一个端。 顶栅电极与底栅电极重叠并与晶体管有源区绝缘。 还提供制造这种晶体管的方法。

    Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same
    20.
    发明申请
    Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same 有权
    具有采用不对称掩埋绝缘层的两种不同操作模式的半导体器件及其制造方法

    公开(公告)号：US20050133789A1

    公开(公告)日：2005-06-23

    申请号：US11011911

    申请日：2004-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L27/10802 ,  H01L27/0214 ,  H01L27/10873 ,  H01L29/7841 ,  H01L29/78612

    摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

    摘要翻译： 根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。 掩埋绝缘层插入在下半导体衬底和上硅图案之间。 穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。 当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时， 漏极电压施加到该区域。