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115 条记录 (耗时 0.029 秒)

    PMD liner nitride films and fabrication methods for improved NMOS performance
    13.
    发明授权
    PMD liner nitride films and fabrication methods for improved NMOS performance 有权
    PMD衬垫氮化物膜和用于改善NMOS性能的制造方法

    公开(公告)号：US07226834B2

    公开(公告)日：2007-06-05

    申请号：US10827692

    申请日：2004-04-19

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/823807 ,  H01L29/665 ,  Y10S438/938

    摘要： Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.

    摘要翻译： 提供半导体器件（102）和制造方法（10），其中在NMOS晶体管上形成氮化物膜（130）以在NMOS晶体管的全部或一部分中施加拉伸应力以改善载流子迁移率。 氮化物层（130）最初以高氢含量在低温下沉积在晶体管上，以在后端处理之前在半导体本体中提供适度的拉伸应力。 随后的后端热处理降低了膜的氢含量并且引起所施加的拉伸应力的增加。

    Transistor fabrication methods using dual sidewall spacers
    14.
    发明授权
    Transistor fabrication methods using dual sidewall spacers 有权
    使用双侧壁间隔件的晶体管制造方法

    公开(公告)号：US07217626B2

    公开(公告)日：2007-05-15

    申请号：US10899360

    申请日：2004-07-26

    申请人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar ,  Lindsey Hall

    发明人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar ,  Lindsey Hall

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

    摘要翻译： 呈现用于晶体管制造的方法（50），其中第一和第二侧壁间隔物（120a，120b）从栅极结构（114）横向向外形成，之后植入源极/漏极区（116）。 方法（50）还包括在注入源极/漏极区域（116）之后去除第二侧壁间隔物（120b）的全部或一部分，其中剩余侧壁间隔物（120a）在源极/漏极植入物之后更窄 改善源极/漏极接触电阻和PMD间隙填充，并促进晶体管沟道中的应力。

    Nitrogen based implants for defect reduction in strained silicon
    15.
    发明申请
    Nitrogen based implants for defect reduction in strained silicon 有权
    用于应变硅缺陷还原的氮基植入物

    公开(公告)号：US20070105294A1

    公开(公告)日：2007-05-10

    申请号：US11268040

    申请日：2005-11-07

    申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas Grider

    发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas Grider

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

    摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

    摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

    Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation
    16.
    发明申请
    Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation 有权
    集成方案，以改善具有多晶硅帽的NMOS，同时减轻PMOS降解

    公开(公告)号：US20060068541A1

    公开(公告)日：2006-03-30

    申请号：US10950138

    申请日：2004-09-24

    申请人： PR Chidambaram ,  Srinivasan Chakravarthi ,  Haowen Bu ,  Rajesh Khamankar

    发明人： PR Chidambaram ,  Srinivasan Chakravarthi ,  Haowen Bu ,  Rajesh Khamankar

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    摘要： A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (212). Offset spacers are formed adjacent to sidewalls of the gate electrodes (216). Extension regions are then formed (214) within the PMOS region and the NMOS region. Sidewall spacers are formed (218) adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (220). A poly cap layer is formed over the device (222) and an anneal or other thermal process is performed (224) that causes the p-type dopant to diffuse into the nitride containing cap oxide layer and obtain a selected dopant profile having sufficient lateral abruptness.

    摘要翻译： 公开了制造半导体器件的方法（200）。 在半导体主体上的栅电极（210）上形成多个氧化物层，以及在PMOS和NMOS区域内限定在半导体本体内的有源区。 在生长的多晶氧化物层（212）上形成含氮化物的氧化物层。 邻近栅电极（216）的侧壁形成偏移间隔物。 然后在PMOS区域和NMOS区域内形成延伸区域（214）。 侧壁间隔件形成（218）邻近门的侧壁。 电极。 将n型掺杂剂注入到NMOS区域中以形成源极/漏极区域，并且将过量剂量的p型掺杂剂注入到PMOS区域中以在PMOS区域（220）内形成源极/漏极区域。 在器件（222）之上形成多晶硅层，并执行退火或其它热处理（224），使得p型掺杂剂扩散到含氮化物的氧化物层中，并获得具有足够横向突变性的选定掺杂剂分布 。

    High performance CMOS transistors using PMD liner stress
    18.
    发明授权
    High performance CMOS transistors using PMD liner stress 有权
    使用PMD衬垫应力的高性能CMOS晶体管

    公开(公告)号：US08809141B2

    公开(公告)日：2014-08-19

    申请号：US11670192

    申请日：2007-02-01

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    IPC分类号： H01L29/739

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

    摘要： A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

    摘要翻译： 在晶体管栅极（40）和源极和漏极区域（70）之上形成硝酸氧化物层（110）。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

    High performance CMOS transistors using PMD liner stress
    20.
    发明申请
    High performance CMOS transistors using PMD liner stress 有权
    使用PMD衬垫应力的高性能CMOS晶体管

    公开(公告)号：US20070128806A1

    公开(公告)日：2007-06-07

    申请号：US11670192

    申请日：2007-02-01

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

    摘要： A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

    摘要翻译： 在晶体管栅极（40）和源极和漏极区域（70）之上形成硝酸氧化物层（110）。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。