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    Advanced contact integration scheme for deep-sub-150 nm devices
    11.
    发明授权
    Advanced contact integration scheme for deep-sub-150 nm devices 有权
    深层次的150纳米器件的高级接触集成方案

    公开(公告)号：US06544888B2

    公开(公告)日：2003-04-08

    申请号：US09892620

    申请日：2001-06-28

    申请人： Brian S. Lee

    发明人： Brian S. Lee

    IPC分类号： H01L2144

    CPC分类号： H01L21/76895 ,  H01L21/28518 ,  H01L21/823871

    摘要： An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicide combined with ion mixing implantation. The contact integration technique realizes junctions having low contact resistance (RC), with ultra-shallow contact junction depth (XJC) and high doping concentration in the silicide contact interface (Nc).

    摘要翻译： 用于深 - 150nm半导体器件（例如W / WN栅电极，双功函数栅极，双栅MOSFET和SOI器件）的先进接触积分技术。 该技术将自对准凸起源极/漏极接触过程与采用W-Salicide结合离子混合植入的方法相结合。 接触积分技术实现了具有低接触电阻（RC）的接点，具有超浅接触结深度（XJC）和硅化物接触界面（Nc）中的高掺杂浓度。

    Differential trench open process
    12.
    发明授权
    Differential trench open process 有权
    差分沟开放过程

    公开(公告)号：US06207573B1

    公开(公告)日：2001-03-27

    申请号：US09314358

    申请日：1999-05-19

    申请人： Brian S. Lee

    发明人： Brian S. Lee

    IPC分类号： H01L21311

    CPC分类号： H01L21/0332 ,  H01L21/3081 ,  H01L21/31144

    摘要： In accordance with the invention, a method for opening holes for semiconductor fabrication includes the steps of providing a pad stack on a substrate, forming a hard mask layer on the pad stack, the hard mask layer selectively removable relative to the pad stack, patterning a resist layer on the hard mask layer, the resist layer being selectively removable relative to the hard mask layer and having a thickness sufficient to prevent scalloping, etching the hard mask layer selective to the resist layer down to the pad stack, removing the resist layer. After removing the resist layer, the pad stack is etched selective to the hard mask layer such that a hole is opened down to the substrate.

    摘要翻译： 根据本发明，一种用于半导体制造的开孔的方法包括以下步骤：在衬底上提供衬垫堆叠，在衬垫堆叠上形成硬掩模层，相对于衬垫叠层选择性地可去除的硬掩模层，图案化 抗蚀剂层相对于硬掩模层可选择性地去除，并且具有足以防止扇形化的厚度，将对抗蚀剂层选择性的硬掩模层蚀刻到焊盘堆叠，去除抗蚀剂层。 在去除抗蚀剂层之后，对硬掩模层选择性地蚀刻焊盘叠层，使得孔向下打开到基板。

    Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same
    14.
    发明授权
    Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same 有权
    具有环线图案结构的半导体器件，用于制造其的交替相移掩模

    公开(公告)号：US07402364B2

    公开(公告)日：2008-07-22

    申请号：US10957678

    申请日：2004-10-05

    申请人： Brian S. Lee ,  Chih-Yu Lee

    发明人： Brian S. Lee ,  Chih-Yu Lee

    IPC分类号： G03F1/00

    CPC分类号： H01L21/32139 ,  G03F1/30 ,  H01L27/10861 ,  H01L27/10891

    摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.

    摘要翻译： 具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。 掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。 通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

    DRAM cell arrangement with vertical MOS transistors
    15.
    发明授权
    DRAM cell arrangement with vertical MOS transistors 有权
    具有垂直MOS晶体管的DRAM单元布置

    公开(公告)号：US07329916B2

    公开(公告)日：2008-02-12

    申请号：US11158439

    申请日：2005-06-22

    申请人： Till Schlösser ,  Brian S. Lee

    发明人： Till Schlösser ,  Brian S. Lee

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10858 ,  H01L27/10852 ,  H01L27/10876

    摘要： The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

    摘要翻译： 本发明涉及具有垂直MOS晶体管的DRAM单元布置。 沿着存储单元矩阵的一列排列的通道区域是由栅介质层包围的肋的部分。 属于一行的MOS晶体管的栅电极是条状字线的一部分，因此在存储单元矩阵的每个交叉点存在垂直双栅极MOS晶体管，其中形成相关联的字线的栅电极 相关肋骨两侧的沟槽。

    Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices
    16.
    发明授权
    Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices 失效
    垂直内部连接的沟槽单元（V-ICTC）和半导体存储器件的形成方法

    公开(公告)号：US06566190B2

    公开(公告)日：2003-05-20

    申请号：US09941689

    申请日：2001-08-30

    申请人： Brian S. Lee ,  John Walsh

    发明人： Brian S. Lee ,  John Walsh

    IPC分类号： H01L2994

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/66181

    摘要： A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.

    摘要翻译： 具有垂直晶体管和内部连接的带（ICS）的动态随机存取存储器（DRAM）器件，用于将晶体管连接到电容器。 ICS不与基板直接接触。 DRAM单元以比常规掩埋带沟槽（BEST）单元所需的电容小得多的单元电容器工作，而不会对器件性能造成任何负面影响。 较低的电池电容也扩大了深沟槽电容器制造技术的可行性，而不需要新的材料或加工方法。 制造DRAM的方法包括在DT单元的顶部上形成非常薄的Si层，同时该方法形成代替传统套环的隔离层。 通过内部热氧化（ITO）形成SOI使得该装置可以完全耗尽。

    Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices
    19.
    发明授权
    Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices 有权
    垂直内部连接的沟槽单元（V-ICTC）和半导体存储器件的形成方法

    公开(公告)号：US06828615B2

    公开(公告)日：2004-12-07

    申请号：US10314131

    申请日：2002-12-09

    申请人： Brian S. Lee ,  John Walsh

    发明人： Brian S. Lee ,  John Walsh

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/1203

    摘要： A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.

    摘要翻译： 具有垂直晶体管和内部连接的带（ICS）的动态随机存取存储器（DRAM）器件，用于将晶体管连接到电容器。 ICS不与基板直接接触。 DRAM单元以比常规掩埋带沟槽（BEST）单元所需的电容小得多的单元电容器工作，而不会对器件性能造成任何负面影响。 较低的电池电容也扩大了深沟槽电容器制造技术的可行性，而不需要新的材料或加工方法。 制造DRAM的方法包括在DT单元的顶部上形成非常薄的Si层，同时该方法形成代替传统套环的隔离层。 通过内部热氧化（ITO）形成SOI使得该装置可以完全耗尽。

    Method for fabricating semiconductor device with loop line pattern structure
    20.
    发明授权
    Method for fabricating semiconductor device with loop line pattern structure 有权
    制造具有环线图形结构的半导体器件的方法

    公开(公告)号：US06818515B1

    公开(公告)日：2004-11-16

    申请号：US10600466

    申请日：2003-06-23

    申请人： Brian S. Lee ,  Chih-Yu Lee

    发明人： Brian S. Lee ,  Chih-Yu Lee

    IPC分类号： H01L21336

    CPC分类号： H01L21/32139 ,  G03F1/30 ,  H01L27/10861 ,  H01L27/10891

    摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip.

    摘要翻译： 具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。 掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区或栅极线。