公开(公告)号：US20070250744A1

公开(公告)日：2007-10-25

申请号：US11407602

申请日：2006-04-19

申请人： Sang Nguyen ,  Hieu Tran ,  Hung Nguyen ,  Phil Klotzkin

发明人： Sang Nguyen ,  Hieu Tran ,  Hung Nguyen ,  Phil Klotzkin

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C2029/3202

摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.

摘要翻译： 在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。 该测试电路电连接到IC的接合焊盘。 在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。 本发明还包括其中闪存芯片的引脚和/或存储单元被顺序发送一系列数据以测试IC的部分连通性的方法。 然后检索顺序发送的数据并将其与原始数据进行比较。 因此，这些数据集之间的差异突出了IC中的连接问题。

公开(公告)号：US20050249006A1

公开(公告)日：2005-11-10

申请号：US10838999

申请日：2004-05-04

申请人： Hieu Tran ,  Sang Nguyen ,  Hung Nguyen

发明人： Hieu Tran ,  Sang Nguyen ,  Hung Nguyen

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/56

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062

摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

摘要翻译： 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。

公开(公告)号：US20060285394A1

公开(公告)日：2006-12-21

申请号：US11487135

申请日：2006-07-14

申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Dang ,  Hung Nguyen ,  Sang Nguyen

发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Dang ,  Hung Nguyen ,  Sang Nguyen

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

公开(公告)号：US20050078526A1

公开(公告)日：2005-04-14

申请号：US10944584

申请日：2004-09-16

申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Nguyen ,  Sang Nguyen

发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Nguyen ,  Sang Nguyen

IPC分类号： G11C16/12 ,  G11C11/34

CPC分类号： G11C16/12

摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

公开(公告)号：US06414522B1

公开(公告)日：2002-07-02

申请号：US09661681

申请日：2000-09-14

申请人： Hung Q. Nguyen ,  Sang Nguyen

发明人： Hung Q. Nguyen ,  Sang Nguyen

IPC分类号： H03C300

CPC分类号： H03K3/354 ,  G05F3/205 ,  G11C5/146 ,  H02M1/36 ,  H02M3/073 ,  H03K3/03

摘要： In an improved charge pump bias generating circuit for a charge pump for a semiconductor integrated circuit device, the pump has a bias generator which has an input for receiving a pump enable signal. The bias generator generates a ramped bias signal in response to the pump enable signal. A voltage controlled oscillator has an input to receive the ramped bias signal and generates an oscillating signal having a frequency which is dependent upon the voltage of the ramped bias signal. As a result, the sudden turn on of the pump enable signal would cause a gradual turn on of the voltage controlled oscillator gradually turning on the clock output signal from the voltage oscillator, thereby reducing power surge in the circuit.

摘要翻译： 在用于半导体集成电路器件的电荷泵的改进的电荷泵偏压产生电路中，该泵具有偏置发生器，其具有用于接收泵使能信号的输入端。 偏置发生器响应于泵使能信号产生斜坡偏置信号。 压控振荡器具有用于接收斜坡偏置信号的输入，并且产生具有取决于斜坡偏置信号的电压的频率的振荡信号。 结果，泵使能信号的突然接通将导致压控振荡器的逐渐导通逐渐接通来自电压振荡器的时钟输出信号，从而减少电路中的电力浪涌。

公开(公告)号：US11904047B1

公开(公告)日：2024-02-20

申请号：US17648845

申请日：2022-01-25

申请人： Sandie Tran ,  Sang Nguyen

发明人： Sandie Tran ,  Sang Nguyen

IPC分类号： A61K9/00 ,  A61K36/9066 ,  A61K9/68 ,  A61K31/165 ,  A61K36/185 ,  A61K36/61 ,  A61K36/54 ,  A61K36/906 ,  A23L33/105 ,  A61K36/81 ,  A61K45/06 ,  A61K36/9068

CPC分类号： A61K9/0056 ,  A23L33/105 ,  A61K9/0058 ,  A61K31/165 ,  A61K36/185 ,  A61K36/54 ,  A61K36/61 ,  A61K36/81 ,  A61K36/906 ,  A61K36/9066 ,  A61K36/9068 ,  A61K45/06

摘要： An herbal composition includes a plurality of herbal components designed to work harmoniously together to alleviate pain and reduce inflammation of the oral mucosa. Such pain and inflammation may be associated with, for example, recurrent aphthous stomatitis. The formulation can include ginger, cayenne, cloves, cinnamon, turmeric, and annatto. The herbal composition may be formulated as a candy or gum, for example, to provide effective delivery to the oral mucosa.

公开(公告)号：US08619459B1

公开(公告)日：2013-12-31

申请号：US13481696

申请日：2012-05-25

申请人： Sang Nguyen ,  Hagop Nazarian

发明人： Sang Nguyen ,  Hagop Nazarian

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C13/004 ,  G11C11/419 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2013/0052 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79

摘要： Providing for resistive random access memory (RRAM) having high read speeds is described herein. By way of example, a RRAM memory can be powered at one terminal by a bitline, and connected at another terminal to a gate of a transistor having a low gate capacitance (relative to a capacitance of the bitline). With this arrangement, a signal applied at the bitline can quickly switch the transistor gate, in response to the RRAM memory being in a conductive state. A sensing circuit configured to measure the transistor can detect a change in current, voltage, etc., of the transistor and determine a state of the RRAM memory from the measurement. Moreover, this measurement can occur very quickly due to the low capacitance of the transistor gate, greatly improving the read speed of RRAM.

摘要翻译： 本文描述了提供具有高读速度的电阻随机存取存储器（RRAM）。 作为示例，RRAM存储器可以通过位线在一个端子供电，并且在另一个端子处连接到具有低栅极电容（相对于位线的电容）的晶体管的栅极。 利用这种布置，响应于RRAM存储器处于导通状态，施加在位线处的信号可以快速地切换晶体管栅极。 配置为测量晶体管的感测电路可以检测晶体管的电流，电压等的变化，并从测量确定RRAM存储器的状态。 此外，由于晶体管栅极的低电容，该测量可能非常快地发生，极大地提高了RRAM的读取速度。