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    Method of programming a non-volatile memory cell to eliminate or to minimize program deceleration
    1.
    发明申请
    Method of programming a non-volatile memory cell to eliminate or to minimize program deceleration 有权
    编程非易失性存储单元以消除或最小化程序减速的方法

    公开(公告)号：US20050078526A1

    公开(公告)日：2005-04-14

    申请号：US10944584

    申请日：2004-09-16

    申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Nguyen ,  Sang Nguyen

    发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Nguyen ,  Sang Nguyen

    IPC分类号： G11C16/12 ,  G11C11/34

    CPC分类号： G11C16/12

    摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

    摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

    Method of programming a non-volatile memory cell to eliminate or to minimize program deceleration
    2.
    发明授权
    Method of programming a non-volatile memory cell to eliminate or to minimize program deceleration 有权
    编程非易失性存储单元以消除或最小化程序减速的方法

    公开(公告)号：US07102930B2

    公开(公告)日：2006-09-05

    申请号：US10944584

    申请日：2004-09-16

    申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Q. Nguyen ,  Sang Thanh Nguyen

    发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Q. Nguyen ,  Sang Thanh Nguyen

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12

    摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

    摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

    Method of programming a non-volatile memory cell by controlling the channel current during the rise period
    3.
    发明授权
    Method of programming a non-volatile memory cell by controlling the channel current during the rise period 有权
    通过在上升期间控制通道电流来对非易失性存储单元进行编程的方法

    公开(公告)号：US07263005B2

    公开(公告)日：2007-08-28

    申请号：US11487135

    申请日：2006-07-14

    申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Q. Nguyen ,  Sang Thanh Nguyen

    发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Q. Nguyen ,  Sang Thanh Nguyen

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12

    摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

    摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

    Method of programming a non-volatile memory cell by controlling the channel current during the rise period
    4.
    发明申请
    Method of programming a non-volatile memory cell by controlling the channel current during the rise period 有权
    通过在上升期间控制通道电流来对非易失性存储单元进行编程的方法

    公开(公告)号：US20060285394A1

    公开(公告)日：2006-12-21

    申请号：US11487135

    申请日：2006-07-14

    申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Dang ,  Hung Nguyen ,  Sang Nguyen

    发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Dang ,  Hung Nguyen ,  Sang Nguyen

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12

    摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

    摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

    Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating
    5.
    发明授权
    Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating 有权
    具有易失性和多位，非易失性功能和操作方法的半导体存储器

    公开(公告)号：US08923052B2

    公开(公告)日：2014-12-30

    申请号：US13196471

    申请日：2011-08-02

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： G11C11/34 ,  G11C14/00 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  H01L27/115 ,  G11C16/04

    CPC分类号： G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

    摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.

    摘要翻译： 描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体 将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 包括第一和第二存储位置的捕获层被配置为将数据彼此独立地存储为非易失性存储器，以及位于捕获层上方的控制栅极。

    Semiconductor memory having electrically floating body transistor
    9.
    发明授权
    Semiconductor memory having electrically floating body transistor 有权
    具有电浮体晶体管的半导体存储器

    公开(公告)号：US08174886B2

    公开(公告)日：2012-05-08

    申请号：US13244839

    申请日：2011-09-26

    申请人： Yuniarto Widjaja ,  Zvi Or-Bach

    发明人： Yuniarto Widjaja ,  Zvi Or-Bach

    IPC分类号： G01C14/00

    CPC分类号： G11C11/404 ,  G11C11/56 ,  G11C11/565 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881

    摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

    摘要翻译： 半导体存储单元包括被配置为被充电到指示存储单元的状态的电平的浮动体区域; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 位于所述第一和第二区域之间的门; 以及背偏置区域，被配置为将电荷注入或从所述浮体区域中提取电荷以维持存储单元的所述状态。 将背偏置施加到背偏置区域将电荷泄漏偏离浮体，并对电池执行保持操作。 单元可以是多级单元。 公开了用于制造存储器件的存储器单元阵列。