利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

55 条记录 (耗时 0.041 秒)

    Amplifier with a gain proportional to power source voltage
    11.
    发明授权
    Amplifier with a gain proportional to power source voltage 失效
    放大器的增益与电源电压成正比

    公开(公告)号：US06972619B2

    公开(公告)日：2005-12-06

    申请号：US10734369

    申请日：2003-12-12

    申请人： Masaharu Sato ,  Takuma Ishida ,  Taku Kobayashi

    发明人： Masaharu Sato ,  Takuma Ishida ,  Taku Kobayashi

    IPC分类号： H03G3/00 ,  H03F1/36

    CPC分类号： H03G3/007

    摘要： In order that an amplifier with a gain proportional to source voltage is obtained, the drain-source voltages of first and second P-channel MOS-FETs are zero-biased, and a voltage shifted higher by the amount of the threshold voltage of the P-channel MOS-FET on the basis of a voltage obtained by dividing the power source voltage by resistors is applied to the positive input terminal of an operational amplifier. The gate of one of the first and second MOS-FETs is connected to a circuit ground, and a negative fixed voltage with reference to the potential obtained by dividing the power source voltage by resistors is applied to the gate of the other MOS-FET. The ON resistances of the two MOS-FETs are used as the input resistor and the feedback resistor of the operational amplifier, respectively.

    摘要翻译： 为了获得具有与源极电压成比例的增益的放大器，第一和第二P沟道MOS-FET的漏极 - 源极电压被零偏置，并且电压偏移到P的阈值电压的量 基于通过将电源电压除以电阻而获得的电压的通道MOS-FET被施加到运算放大器的正输入端。 第一和第二MOS-FET中的一个的栅极连接到电路地，并且参考通过用电阻分压电源电压而获得的电位的负固定电压被施加到另一MOS-FET的栅极。 两个MOS-FET的导通电阻分别用作运算放大器的输入电阻和反馈电阻。

    Current detection type sense amplifier
    12.
    发明授权
    Current detection type sense amplifier 失效
    电流检测型读出放大器

    公开(公告)号：US6151261A

    公开(公告)日：2000-11-21

    申请号：US99525

    申请日：1998-06-18

    申请人： Masaharu Sato

    发明人： Masaharu Sato

    IPC分类号： G11C11/416 ,  G11C7/06 ,  G11C11/419 ,  H01L27/10 ,  G11C7/02

    CPC分类号： G11C11/419 ,  G11C7/067 ,  G11C2207/063

    摘要： The invention provides a high speed sense amplifier of the current detection type employing NPN transistors used for a static operation type RAM which allows high integration and can suppress increase of power dissipation and deterioration in speed even in a high integration condition. Pairs of bit lines to which data of memory cells of a static type RAM are connected are connected to a pair of common data lines through MOS transistors, and the emitter terminals of a pair of bipolar transistors are connected to the data lines while the collector terminals which serve as signal output terminals of the sense amplifier are connected to a first power supply through resistors and the base terminals are connected to a second power supply. Further, a pair of resistance elements for normally supplying current to the sense amplifier therethrough are connected to the emitter terminals of the bipolar transistors.

    摘要翻译： 本发明提供一种使用用于静态操作型RAM的NPN晶体管的电流检测型高速感测放大器，其允许高集成度，并且即使在高集成条件下也能够抑制功率消耗的增加和速度的劣化。 连接静态RAM的存储单元的数据的位线对通过MOS晶体管连接到一对公共数据线，并且一对双极晶体管的发射极端子连接到数据线，而集电极端子 用作读出放大器的信号输出端的电阻器通过电阻器连接到第一电源，并且基极端子连接到第二电源。 此外，用于通过其通常向读出放大器供电的一对电阻元件连接到双极晶体管的发射极端子。

    Clocked flip flop circuit with built-in clock controller and frequency divider using the same
    13.
    发明授权
    Clocked flip flop circuit with built-in clock controller and frequency divider using the same 失效
    时钟触发电路采用内置时钟控制器和分频器

    公开(公告)号：US5945858A

    公开(公告)日：1999-08-31

    申请号：US50350

    申请日：1998-03-31

    申请人： Masaharu Sato

    发明人： Masaharu Sato

    IPC分类号： H03K3/3562 ,  H03K3/356

    CPC分类号： H03K3/356113

    摘要： A clocked master slave flip flop circuit includes a current mirror circuit with a pair of field effect transistors serving as a constant current source, and the field effect transistors are gated by a clock signal and a complementary clock signal; and the clocked master slave flip flop circuit further includes a built-in logic circuits achieving logic functions inverse to each other, and one the built-in logic circuits and the other field effect transistor are connected in series of one of the field effect transistors and in parallel to the other field effect transistor; the logic circuits are responsive to a clock control signal so as to enable the constant current source, and causes the clocked master slave flip flop circuit to change or maintain a data bit stored therein.

    摘要翻译： 时钟控制主从触发电路包括具有一对场效应晶体管的电流镜电路，用作恒流源，场效应晶体管由时钟信号和互补时钟信号选通; 并且时钟控制的主从触发器电路还包括实现彼此相反的逻辑功能的内置逻辑电路，并且内置的逻辑电路和另一个场效应晶体管中的一个串联连接一个场效应晶体管， 并联其他场效应晶体管; 逻辑电路响应于时钟控制信号，以使能恒定电流源，并使时钟控制的主从触发器电路改变或维持其中存储的数据位。

    Tone generator system for an electronic organ
    17.
    发明授权
    Tone generator system for an electronic organ 失效
    电子琴发声系统

    公开(公告)号：US4056033A

    公开(公告)日：1977-11-01

    申请号：US622383

    申请日：1975-10-14

    申请人： Michihiro Inoue ,  Takeji Kimura ,  Masaharu Sato ,  Masahiko Tsunoo

    发明人： Michihiro Inoue ,  Takeji Kimura ,  Masaharu Sato ,  Masahiko Tsunoo

    IPC分类号： G10H1/08 ,  G10H5/10 ,  G10H1/02

    CPC分类号： G10H5/10 ,  G10H1/08

    摘要： A tone generator system for an electronic organ which is capable of being fabricated into an LSI structure and receives a saw-tooth wave or staircase wave as an input thereto comprises a frequency divider for the saw-tooth wave or staircase wave including a ladder resistor network and a complementary MOS FET devices, an analog switch having a wide dynamic range and a high linearity in input-output transfer characteristic constructed by MOS FET devices to serve as an indirect keying means, a sustain means including a novel structure of a variable impedance element which is constructed to control a channel current in a MOS FET device by varying the potential distribution in the source region, and an impedance coverter constructed by complementary MOS FET devices and free from a D.C. level shift. With the above arrangement a tone generator system of high quality for an electronic organ is provided.

    摘要翻译： 一种能够制造成LSI结构并接收锯齿波或阶梯波作为输入的电子琴的音调发生器系统包括用于锯齿波的分频器或包括梯形电阻网络的阶梯波 以及互补MOS FET器件，具有由MOS FET器件构成的用作间接键控装置的输入输出传输特性中的宽动态范围和高线性度的模拟开关，包括可变阻抗元件的新颖结构的维持装置 其被构造为通过改变源区域中的电位分布来控制MOS FET器件中的沟道电流，以及由互补MOS FET器件构成并且没有DC电平偏移的阻抗覆盖器。 通过上述配置，提供了一种用于电子机器的高品质音调发生器系统。

    Room temperature-curable organopolysiloxane compositions
    19.
    发明申请
    Room temperature-curable organopolysiloxane compositions 有权
    室温可固化的有机聚硅氧烷组合物

    公开(公告)号：US20060258818A1

    公开(公告)日：2006-11-16

    申请号：US11409041

    申请日：2006-04-24

    申请人： Tsuneo Kimura ,  Masaharu Sato

    发明人： Tsuneo Kimura ,  Masaharu Sato

    IPC分类号： C08L83/04 ,  B32B27/00

    CPC分类号： C08L83/06 ,  C08L83/00

    摘要： RTV organopolysiloxane compositions comprising (A) a diorganopolysiloxane having hydroxyl or alkoxysilyl groups at both ends, (B) a polyoxypropylene-modified silicone, (C) wet silica, and (D) a silane or siloxane having at least three silicon-bonded hydrolyzable groups have improved sag control and cure at room temperature into products with improved rubber physical properties and durability.

    摘要翻译： RTV有机聚硅氧烷组合物，其包含（A）在两端具有羟基或烷氧基甲硅烷基的二有机聚硅氧烷，（B）聚氧丙烯改性硅氧烷，（C）湿二氧化硅和（D）具有至少三个硅键合的可水解基团的硅烷或硅氧烷 在室温下将下垂控制和固化改进成具有改进的橡胶物理性能和耐久性的产品。

    Semiconductor device
    20.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20060091497A1

    公开(公告)日：2006-05-04

    申请号：US11302399

    申请日：2005-12-14

    申请人： Masaharu Sato

    发明人： Masaharu Sato

    IPC分类号： H01L27/082

    CPC分类号： H01L29/66272 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/7322

    摘要： A semiconductor device 100 includes a transistor, through which an electrical current flows via a first N-type buried region 106 and a second N-type buried region 108 having a conductivity type same as an N-type collector region 118 has. In semiconductor device 100, an N-type coupling region 107 that is a portion forming a second conductivity type region by an impact ionization when the transistor is in an operating state, is disposed on a path including the N-type collector region 118, the first N-type buried region 106 and the second N-type buried region 108.

    摘要翻译： 半导体器件100包括经由第一N型掩埋区域106流过电流的晶体管和具有与N型集电极区域118相同的导电类型的第二N型掩埋区域108。 在半导体装置100中，作为在晶体管处于工作状态时通过冲击电离形成第二导电类型区域的部分的N型耦合区域107设置在包括N型集电区域118的路径上 第一N型掩埋区域106和第二N型掩埋区域108。