利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

80 条记录 (耗时 0.031 秒)

    Memory access buffer and reordering apparatus using priorities
    12.
    发明授权
    Memory access buffer and reordering apparatus using priorities 失效
    使用优先级的存储器访问缓冲器和重新排序装置

    公开(公告)号：US6145065A

    公开(公告)日：2000-11-07

    申请号：US67899

    申请日：1998-04-29

    申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Yutaka Terada ,  Takashi Hirata

    发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Yutaka Terada ,  Takashi Hirata

    IPC分类号： G06F13/16 ,  G06F12/02

    CPC分类号： G06F13/1631

    摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.

    摘要翻译： 目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。 为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问 主存储部分不管数据传输，从而流水线地址输入周期。 此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与 相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。 这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

    Network apparatus
    14.
    发明授权
    Network apparatus 有权
    网络设备

    公开(公告)号：US06919652B2

    公开(公告)日：2005-07-19

    申请号：US10035434

    申请日：2002-01-04

    申请人： Satoshi Takahashi ,  Takashi Hirata ,  Hironori Akamatsu ,  Yoshihide Komatsu ,  Koichi Sugimoto

    发明人： Satoshi Takahashi ,  Takashi Hirata ,  Hironori Akamatsu ,  Yoshihide Komatsu ,  Koichi Sugimoto

    IPC分类号： G06F1/26 ,  G06F13/40 ,  H01H3/26

    CPC分类号： G06F1/266 ,  G06F13/4072 ,  Y10T307/50 ,  Y10T307/76 ,  Y10T307/937 ,  Y10T307/944

    摘要： A network apparatus is provided, which allows another network apparatus to recognize the disconnection with reliability, if a power supply to the network apparatus is interrupted. A control unit operating with a first power supply outputs a first signal, which is level-converted and supplied as a second signal to an intermediate potential supply unit operating with a second power supply. In the intermediate potential supply unit, a switch receives a reset signal as a switch signal and outputs, when the power supply is interrupted, a ground potential to a driver instead of the second signal. As a result, an intermediate potential supplied to a cable is forcibly set to the ground potential.

    摘要翻译： 如果网络设备的电源中断，则提供一种网络设备，其允许另一网络设备以可靠性识别该断开。 与第一电源一起操作的控制单元输出第一信号，该第一信号被电平转换并作为第二信号提供给与第二电源一起操作的中间电位供应单元。 在中间电位供给单元中，开关接收复位信号作为开关信号，并且当电源中断时，输出对驱动器的接地电位而不是第二信号。 结果，提供给电缆的中间电势被强制设定为地电位。

    Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system
    15.
    发明授权
    Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system 失效
    具有电压检测电路和信号发射和接收系统的半导体集成电路

    公开(公告)号：US06944003B2

    公开(公告)日：2005-09-13

    申请号：US10365527

    申请日：2003-02-13

    申请人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

    发明人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

    IPC分类号： G01R31/28 ,  H01L21/66 ,  H02H9/04 ,  H02H3/24

    CPC分类号： H02H9/046

    摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.

    摘要翻译： 第一半导体集成电路通过电缆连接到第二半导体集成电路。 在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。 第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。 在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作 强制。 因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。 因此，在低电压条件下可以进行运行评估。

    Memory circuit and method of generating the same
    16.
    发明授权
    Memory circuit and method of generating the same 有权
    存储电路及其生成方法

    公开(公告)号：US07187573B2

    公开(公告)日：2007-03-06

    申请号：US11011116

    申请日：2004-12-15

    申请人： Yutaka Terada ,  Hironori Akamatsu

    发明人： Yutaka Terada ,  Hironori Akamatsu

    IPC分类号： G11C5/06

    CPC分类号： G11C7/1006 ,  G11C7/10 ,  G11C2207/104 ,  H01L27/10897

    摘要： A memory circuit 10 includes: a feed-through input terminal 13 for inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuit 14 provided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal 13; and a feed-through output terminal 15 for outputting the signal relayed by the intermediate buffer circuit 14. Connections between the feed-through input terminal 13 and the intermediate buffer circuit 14 and between the intermediate buffer circuit 14 and the feed-through output terminal 15 are established by feed-through wires 16, 17, respectively. The feed-through wires 16, 17 are not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.

    摘要翻译： 存储电路10包括：馈通输入端13，用于在读取和写入存储单元时输入与要输入的信号不同的信号; 设置在存储单元布置的区域之间的中间缓冲电路14，用于中继通过馈通输入端13输入的信号; 以及用于输出由中间缓冲电路14中继的信号的馈通输出端子15。 直通输入端子13和中间缓冲电路14之间以及中间缓冲电路14与馈通输出端子15之间的连接分别由馈通线16,17建立。 当读取和布线存储单元或存储单元时，馈通线16,17不连接到要使用的导线。

    Memory circuit and method of generating the same
    17.
    发明申请
    Memory circuit and method of generating the same 有权
    存储电路及其生成方法

    公开(公告)号：US20050128818A1

    公开(公告)日：2005-06-16

    申请号：US11011116

    申请日：2004-12-15

    申请人： Yutaka Terada ,  Hironori Akamatsu

    发明人： Yutaka Terada ,  Hironori Akamatsu

    IPC分类号： G11C11/41 ,  G11C5/00 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G11C7/1006 ,  G11C7/10 ,  G11C2207/104 ,  H01L27/10897

    摘要： A memory circuit 10 includes: a feed-through input terminal 13 for inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuit 14 provided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal 13; and a feed-through output terminal 15 for outputting the signal relayed by the intermediate buffer circuit 14. Connections between the feed-through input terminal 13 and the intermediate buffer circuit 14 and between the intermediate buffer circuit 14 and the feed-through output terminal 15 are established by feed-through wires 16, 17, respectively. The feed-through wires 16, 17 are not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.

    摘要翻译： 存储电路10包括：馈通输入端13，用于在读取和写入存储单元时输入与要输入的信号不同的信号; 设置在存储单元布置的区域之间的中间缓冲电路14，用于中继通过馈通输入端13输入的信号; 以及用于输出由中间缓冲电路14中继的信号的馈通输出端子15。 直通输入端子13和中间缓冲电路14之间以及中间缓冲电路14与馈通输出端子15之间的连接分别由馈通线16,17建立。 当读取和布线存储单元或存储单元时，馈通线16,17不连接到要使用的导线。

    Semiconductor mounting system and semiconductor chip
    18.
    发明授权
    Semiconductor mounting system and semiconductor chip 失效
    半导体安装系统和半导体芯片

    公开(公告)号：US06163459A

    公开(公告)日：2000-12-19

    申请号：US122566

    申请日：1998-07-24

    申请人： Yutaka Terada ,  Hironori Akamatsu

    发明人： Yutaka Terada ,  Hironori Akamatsu

    IPC分类号： H01L25/10 ,  H05K1/14

    CPC分类号： H05K1/14 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2225/1029 ,  H01L2924/01055 ,  H01L2924/14 ,  H05K1/145 ,  H01L2924/00014

    摘要： A semiconductor mounting system of the present invention includes a first semiconductor chip in which a first semiconductor integrated circuit is packaged and a second semiconductor chip in which a second semiconductor integrated circuit is packaged. The first semiconductor chip includes a plurality of first pins provided on a first surface and a plurality of second pins provided on a second surface. The second semiconductor chip includes a plurality of third pins provided on a third surface and a plurality of fourth pins provided on a fourth surface. The semiconductor mounting system further includes: a plurality of first lines for electrically connecting the first pins with the third pins; and a plurality of second lines for electrically connecting the second pins with the fourth pins. A length of the first lines is substantially equal to a length of the second lines.

    摘要翻译： 本发明的半导体安装系统包括封装有第一半导体集成电路的第一半导体芯片和封装有第二半导体集成电路的第二半导体芯片。 第一半导体芯片包括设置在第一表面上的多个第一引脚和设置在第二表面上的多个第二引脚。 第二半导体芯片包括设置在第三表面上的多个第三引脚和设置在第四表面上的多个第四引脚。 半导体安装系统还包括：多个用于将第一引脚与第三引脚电连接的第一线; 以及用于将第二引脚与第四引脚电连接的多条第二线。 第一行的长度基本上等于第二行的长度。

    Memory macro and semiconductor integrated circuit
    19.
    发明授权
    Memory macro and semiconductor integrated circuit 有权

    公开(公告)号：US06831356B2

    公开(公告)日：2004-12-14

    申请号：US10701422

    申请日：2003-11-06

    申请人： Yutaka Terada ,  Hironori Akamatsu

    发明人： Yutaka Terada ,  Hironori Akamatsu

    IPC分类号： H01L2352

    CPC分类号： H01L27/0203 ,  G11C5/025 ,  H01L27/105

    摘要： A memory array portion, a connection circuit serving as an interface of the memory array portion and a signal wiring connecting the memory array portion to the connection circuit are provided. Mesh wirings comprising first and second wiring layers are provided on the memory array portion. The connection circuit is connected to a plurality of signal lines comprising a third wiring layer provided on the memory array portion, the connection circuit or the signal wiring, through an intermediate wiring comprising the second wiring layer. The region where the intermediate wiring is provide on the memory array portion or on the signal wiring, and the mesh wiring comprising the second wiring layer is not present on the region where the intermediate wiring is provided.