公开(公告)号：US06668266B2

公开(公告)日：2003-12-23

申请号：US09973734

申请日：2001-10-11

申请人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F738

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30043

摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

摘要翻译： 在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加 防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

公开(公告)号：US5832258A

公开(公告)日：1998-11-03

申请号：US364418

申请日：1994-12-27

申请人： Atsushi Kiuchi ,  Toru Baji

发明人： Atsushi Kiuchi ,  Toru Baji

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F15/78

CPC分类号： G06F9/3802 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/382

摘要： A digital signal processor that includes an execution unit, a condition code register, a program memory, a program control unit, and an instruction decoder. The program memory stores a sequence of instruction words and includes an instruction word that has at least one field that identifies a data processing operation to be performed by the execution unit. The instruction word also includes a condition code field that identifies a predefined condition and also identifies whether said condition code register should be updated when the data processing operation is performed by the execution unit. The program control unit outputs an instruction address to the program memory so as to select the instruction word in the program memory. The instruction decoder decodes the selected instruction word. It includes decoder circuitry for decoding the at least one field to generate control signals for controlling the execution unit to perform the specific data processing operation. The execution unit includes means for generating a current condition code flag if a corresponding predefined condition occurs when the execution unit performs the current data processing operation in response to the control signals. The instruction decoder further includes condition code decoder circuitry for decoding the condition code field to generate a control signal for enabling and disabling the condition code register to store the current condition code flag in accordance with the condition code field's value.

摘要翻译： 一种数字信号处理器，包括执行单元，条件码寄存器，程序存储器，程序控制单元和指令译码器。 程序存储器存储指令字序列，并且包括具有标识要由执行单元执行的数据处理操作的至少一个字段的指令字。 指令字还包括识别预定义条件的条件码字段，并且还识别当执行单元执行数据处理操作时是否应当更新所述条件码寄存器。 程序控制单元向程序存储器输出指令地址，以便选择程序存储器中的指令字。 指令译码器解码所选择的指令字。 它包括解码器电路，用于解码至少一个场以产生用于控制执行单元执行特定数据处理操作的控制信号。 执行单元包括当执行单元响应于控制信号执行当前数据处理操作而发生相应的预定条件时，生成当前条件码标志的装置。 指令解码器还包括条件码解码器电路，用于对条件代码字段进行解码，以产生用于根据条件代码字段的值来产生和禁用状态代码寄存器来存储当前条件代码标志的控制信号。

公开(公告)号：US5535417A

公开(公告)日：1996-07-09

申请号：US127429

申请日：1993-09-27

申请人： Toru Baji ,  Atsushi Kiuchi

发明人： Toru Baji ,  Atsushi Kiuchi

IPC分类号： G06F13/28 ,  G06F15/78 ,  G06F17/10

CPC分类号： G06F13/28

摘要： A single chip digital signal processor (DSP) includes memory mapped resources and an on-chip direct memory access controller (DMAC). The memory mapped resources of the DSP include an on-chip program memory, an on-chip data memory, internal registers and memory mapped external memories and peripheral devices. The DMAC includes a host computer interface that processes host originated data transfer commands for transferring data to and from memory mapped resources of the DSP, and commands for setting the mode of operation of the DSP. The DMAC also has a dedicated interrupt controller for handling interrupts from a host computer and from peripheral devices. The DMAC processes interrupts from the host while a primary direct memory access transfer is being performed by the DMAC without having to store address register and count register information in a memory stacking area. As a result, the DMAC can switch from a primary DMA transfer to a host data transfer and back without using any instruction cycles for "overhead" associated with storing and restoring registers in a memory stacking area. The DMAC's host interface is also designed to be connected to a byte-structured boot ROM and the DMAC includes a boot sequencer for automatically loading a boot program from the ROM into the DMAC's on-chip instruction memory whenever the DSP is reset and a boot ROM is connected to the host interface.

摘要翻译： 单芯片数字信号处理器（DSP）包括存储器映射资源和片上直接存储器存取控制器（DMAC）。 DSP的存储器映射资源包括片上程序存储器，片上数据存储器，内部寄存器和存储器映射的外部存储器和外围设备。 DMAC包括一个主计算机接口，处理主机发起的数据传输命令，用于从DSP的存储器映射资源传输数据，以及用于设置DSP操作模式的命令。 DMAC还具有专用的中断控制器，用于处理来自主机和外围设备的中断。 当DMAC正在执行主直接存储器访问传输时，DMAC处理来自主机的中断，而不必将地址寄存器和计数寄存器信息存储在存储器堆叠区域中。 因此，DMAC可以从主DMA传输切换到主机数据传输并返回，而不使用与在存储器堆叠区域中存储和恢复寄存器相关联的“开销”的任何指令周期。 DMAC的主机接口还被设计为连接到字节结构的引导ROM，并且DMAC包括引导顺控程序，用于在DSP复位时自动将引导程序从ROM加载到DMAC的片上指令存储器中，并且启动ROM 连接到主机接口。

公开(公告)号：US5638524A

公开(公告)日：1997-06-10

申请号：US443199

申请日：1995-05-17

申请人： Atsushi Kiuchi ,  Toru Baji ,  Tetsuya Nakagawa ,  Kenji Kaneko

发明人： Atsushi Kiuchi ,  Toru Baji ,  Tetsuya Nakagawa ,  Kenji Kaneko

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3822

摘要： A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the instruction memory so as to select one instruction word in the instruction memory. Every DSP instruction word identifies one data processing operation and one data transfer operation to be performed. The DSP instruction words include a predefined DSP instruction word having separate source and destination fields for specifying register locations for data sources and data destinations. The RISC instruction words include a predefined RISC instruction word corresponding to the predefined DSP instruction word. The predefined RISC instruction word has separate source and destination fields for specifying register locations for data sources and data destinations. One of the source and destination fields in the predefined RISC instruction word has more bits than the corresponding field in the predefined DSP instruction word. The instruction decoder decodes the selected instruction.

摘要翻译： 一种包括指令存储器，程序控制单元和指令译码器的数字信号处理器。 指令存储器存储包括DSP指令字和RISC指令字的指令字序列。 程序控制单元向指令存储器输出指令地址，以便在指令存储器中选择一个指令字。 每个DSP指令字标识要执行的一个数据处理操作和一个数据传送操作。 DSP指令字包括具有用于指定数据源和数据目的地的寄存器位置的独立源和目的地字段的预定义DSP指令字。 RISC指令字包括与预定义的DSP指令字对应的预定RISC指令字。 预定义的RISC指令字具有用于指定数据源和数据目的地的寄存器位置的单独的源和目标字段。 预定义RISC指令字中的源和目标字段之一具有比预定义DSP指令字中相应字段更多的位。 指令译码器解码所选择的指令。

公开(公告)号：US20120105679A1

公开(公告)日：2012-05-03

申请号：US13274324

申请日：2011-10-15

申请人： Hiroshi OSUGA ,  Takaaki Suzuki ,  Atsushi Kiuchi ,  Kazuhide Kawade ,  Hiroyuki Hamasaki

发明人： Hiroshi OSUGA ,  Takaaki Suzuki ,  Atsushi Kiuchi ,  Kazuhide Kawade ,  Hiroyuki Hamasaki

IPC分类号： H04N5/217 ,  H04N5/76

CPC分类号： G06T5/006 ,  G06T2200/28 ,  G06T2207/10004 ,  H04N5/2173 ,  H04N5/23238 ,  H04N5/247 ,  H04N5/357 ,  H04N5/3572 ,  H04N5/77 ,  H04N5/907

摘要： The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.

摘要翻译： 提供本发明以在将由多个摄像机捕获的图像数据存储到半导体存储器的情况下减少总线上的负载。 对于半导体集成电路，可以耦合多个摄像机和半导体存储器。 半导体集成电路包括多个第一接口，第二接口，总线和多个图像处理模块。 图像处理模块包括对预先指定区域中的图像数据进行失真校正的处理，并且经过失真校正的区域中的图像数据经由总线和第二接口写入半导体存储器。 通过从图像处理模块中的失真校正对象中排除预先指定区域之外的图像数据，减少了传送到半导体存储器的图像数据量。

公开(公告)号：US06185212B2

公开(公告)日：2001-02-06

申请号：US09056770

申请日：1998-04-08

申请人： Kenichi Sakamoto ,  Akio Makimoto ,  Akihiko Takase ,  Norihiko Moriwaki ,  Atsushi Kiuchi

发明人： Kenichi Sakamoto ,  Akio Makimoto ,  Akihiko Takase ,  Norihiko Moriwaki ,  Atsushi Kiuchi

IPC分类号： H04L1228

CPC分类号： H04L49/254 ,  H04L49/30 ,  H04L2012/5681

摘要： An ATM cell processing apparatus including a DRAM for a frame producing buffer of a frame producing unit. In order to absorb the anisotropy of the access rate of the DRAM access, the random access mode of the DRAM access is always used. To compensate a drop in access rate in this case, the DRAM is arranged is an array form and each cell is divided. Resultant partial cell data are written into and read from respective DRAM banks in order. As a result, a fast cell buffer having a large capacity can be formed. The present cell buffer can be applied to a FIFO and the like as well.

摘要翻译： 一种ATM信元处理装置，包括用于帧产生单元的帧产生缓冲器的DRAM。 为了吸收DRAM访问的访问速率的各向异性，始终使用DRAM访问的随机存取模式。 为了补偿这种情况下的访问速率的下降，DRAM被排列成阵列形式，并且每个单元被分割。 所产生的部分单元数据按顺序写入和从相应的DRAM存储体读取。 结果，可以形成具有大容量的快速电池缓冲器。 本单元缓冲器也可以应用于FIFO等。

公开(公告)号：US4896104A

公开(公告)日：1990-01-23

申请号：US311161

申请日：1989-02-15

申请人： Chandravadan N. Patel ,  Richard Wm. Blasco ,  Atsushi Kiuchi ,  Hiromitsu Inada

发明人： Chandravadan N. Patel ,  Richard Wm. Blasco ,  Atsushi Kiuchi ,  Hiromitsu Inada

IPC分类号： G06F7/02 ,  G01R19/04

CPC分类号： G01R19/04

摘要： A digital peak and valley detector including a peak value address register, a valley value address register, a peak value data register, a valley value data register, a peak comparator for comparing the value stored in the peak value data register with value data contained in the digital signal applied to the digital peak and valley detector and for causing the greater of the two to be stored in the peak value data register while simultaneously storing the address in the peak value address register and a valley comparator for comparing the valley value contained in the valley value data register with the value data contained in the digital signal applied to the digital peak and valley detector for determining which is less and for causing the value and the address of the smaller of the two to be stored respectively in the valley value data and the valley value address registers.

摘要翻译： 数字峰谷检测器，包括峰值地址寄存器，谷值地址寄存器，峰值数据寄存器，谷值数据寄存器，用于将存储在峰值数据寄存器中的值与包含在其中的值数据进行比较的峰值比较器 数字信号施加到数字峰谷检测器，并使两个中的较大值存储在峰值数据寄存器中，同时将地址存储在峰值地址寄存器和谷比较器中，用于比较包含在 谷数值数据寄存器，其中包含在数字信号中的数值数据被加到数字峰谷检测器，用于确定哪一个较小，并且使两个中较小的值的值和地址分别存储在谷值数据中 和谷值地址寄存器。

公开(公告)号：US4809206A

公开(公告)日：1989-02-28

申请号：US87346

申请日：1987-08-20

申请人： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Hirotada Ueda

发明人： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Hirotada Ueda

IPC分类号： G06F9/34 ,  G06F7/544 ,  G06F12/02 ,  G06F17/10 ,  H03H17/02 ,  G06F7/38

CPC分类号： G06F7/5443

摘要： This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.Contrivances are made in order to set the number of a plurality of data that are stored in the data memory for repetition of use, to an arbitrary value.

摘要翻译： 本发明涉及诸如数字信号处理器的信息处理设备，并且特别适用于数字滤波器。 从初始值数据到与数字滤波器的滤波系数相关的最终值数据的多个数据被存储在数据存储器中，并且通过地址运算单元的增量操作被依次读出。 数据运算单元依次执行依次读出的多个数据和顺序输入的数字输入信号的乘积和/或和运算，进行数字信号处理。 该信息处理装置特别地具有如下装置：当访问地址从初始值开始时，由于增量操作而超过最终值并达到返回地址，自动将访问地址返回到初始值。 因此，可以重复使用存储在数据存储器中的多个数据。 为了将存储在用于重复使用的数据存储器中的多个数据的数量设置为任意值，进行了操作。

公开(公告)号：US09071750B2

公开(公告)日：2015-06-30

申请号：US13274324

申请日：2011-10-15

申请人： Hiroshi Osuga ,  Takaaki Suzuki ,  Atsushi Kiuchi ,  Kazuhide Kawade ,  Hiroyuki Hamasaki

发明人： Hiroshi Osuga ,  Takaaki Suzuki ,  Atsushi Kiuchi ,  Kazuhide Kawade ,  Hiroyuki Hamasaki

IPC分类号： H04N5/76 ,  H04N7/18 ,  H04L12/50 ,  H04N5/232 ,  H04N5/247 ,  H04N5/357 ,  H04N5/77 ,  H04N5/907

CPC分类号： G06T5/006 ,  G06T2200/28 ,  G06T2207/10004 ,  H04N5/2173 ,  H04N5/23238 ,  H04N5/247 ,  H04N5/357 ,  H04N5/3572 ,  H04N5/77 ,  H04N5/907

摘要： The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.

摘要翻译： 提供本发明以在将由多个摄像机捕获的图像数据存储到半导体存储器的情况下减少总线上的负载。 对于半导体集成电路，可以耦合多个摄像机和半导体存储器。 半导体集成电路包括多个第一接口，第二接口，总线和多个图像处理模块。 图像处理模块包括对预先指定区域中的图像数据进行失真校正的处理，并且经过失真校正的区域中的图像数据经由总线和第二接口写入半导体存储器。 通过从图像处理模块中的失真校正对象中排除预先指定区域之外的图像数据，减少了传送到半导体存储器的图像数据量。

公开(公告)号：US06505295B1

公开(公告)日：2003-01-07

申请号：US09367536

申请日：1999-08-16

申请人： Mitsuru Hiraki ,  Atsushi Kiuchi ,  Kesami Hagiwara

发明人： Mitsuru Hiraki ,  Atsushi Kiuchi ,  Kesami Hagiwara

IPC分类号： G06F940

CPC分类号： G06F9/381 ,  G06F9/325

摘要： To provide a data processing apparatus equipped with a control means to reduce the power required for memory accessing, in spite of the unavailability of a repeat instruction, by reading instructions reiteratively from a small scale buffer in loop processing. Also to provide a data processing apparatus equipped with a means to opt to apply, or not to apply, control to read instructions, that have to be executed reiteratively in loop processing, out of a small scale buffer reiteratively. If, as a result of execution of an instruction to alter the content of a certain register prior to a series of instructions to be executed reiteratively, the register satisfies a specific condition, the series of instructions to be executed repeatedly are read out of a small scale buffer reiteratively. A data processing apparatus equipped with a control means to reduce the power required for memory accessing, in spite of the unavailability of a repeat instruction, by reading instructions reiteratively from a small scale buffer in loop processing can be provided. Also a data processing apparatus equipped with a means to opt to apply, or not to apply, control to read instructions, that have to be executed reiteratively in loop processing, out of a small scale buffer reiteratively can be provided.

摘要翻译： 为了提供一种配备有控制装置的数据处理装置，尽管重复指令不可用，通过在循环处理中从小规模缓冲器重复读取指令来减少存储器访问所需的功率。 还提供一种数据处理装置，其配备有选择适用于或不应用控制读取必须在循环处理中重复执行的指令的装置，重复地从小规模缓冲器中执行。如果由于 在一系列要执行的指令之前执行改变某个寄存器的内容的指令，重复地，寄存器满足特定条件，重复执行的一系列指令被重复地从小规模缓冲器中读出.A数据 可以提供配备有控制装置的处理装置，尽管重复指令不可用，通过在循环处理中从小规模缓冲器重复读取指令来减少存储器访问所需的功率。 另外，可以提供一种数据处理装置，该装置具有选择适用于或不应用控制读取必须在循环处理中重复执行的指令的装置。