-
公开(公告)号:US06505295B1
公开(公告)日:2003-01-07
申请号:US09367536
申请日:1999-08-16
申请人: Mitsuru Hiraki , Atsushi Kiuchi , Kesami Hagiwara
发明人: Mitsuru Hiraki , Atsushi Kiuchi , Kesami Hagiwara
IPC分类号: G06F940
摘要: To provide a data processing apparatus equipped with a control means to reduce the power required for memory accessing, in spite of the unavailability of a repeat instruction, by reading instructions reiteratively from a small scale buffer in loop processing. Also to provide a data processing apparatus equipped with a means to opt to apply, or not to apply, control to read instructions, that have to be executed reiteratively in loop processing, out of a small scale buffer reiteratively. If, as a result of execution of an instruction to alter the content of a certain register prior to a series of instructions to be executed reiteratively, the register satisfies a specific condition, the series of instructions to be executed repeatedly are read out of a small scale buffer reiteratively. A data processing apparatus equipped with a control means to reduce the power required for memory accessing, in spite of the unavailability of a repeat instruction, by reading instructions reiteratively from a small scale buffer in loop processing can be provided. Also a data processing apparatus equipped with a means to opt to apply, or not to apply, control to read instructions, that have to be executed reiteratively in loop processing, out of a small scale buffer reiteratively can be provided.
摘要翻译: 为了提供一种配备有控制装置的数据处理装置,尽管重复指令不可用,通过在循环处理中从小规模缓冲器重复读取指令来减少存储器访问所需的功率。 还提供一种数据处理装置,其配备有选择适用于或不应用控制读取必须在循环处理中重复执行的指令的装置,重复地从小规模缓冲器中执行。如果由于 在一系列要执行的指令之前执行改变某个寄存器的内容的指令,重复地,寄存器满足特定条件,重复执行的一系列指令被重复地从小规模缓冲器中读出.A数据 可以提供配备有控制装置的处理装置,尽管重复指令不可用,通过在循环处理中从小规模缓冲器重复读取指令来减少存储器访问所需的功率。 另外,可以提供一种数据处理装置,该装置具有选择适用于或不应用控制读取必须在循环处理中重复执行的指令的装置。
-
公开(公告)号:US07080240B2
公开(公告)日:2006-07-18
申请号:US10302850
申请日:2002-11-25
申请人: Mitsuru Hiraki , Atsushi Kiuchi , Kesami Hagiwara
发明人: Mitsuru Hiraki , Atsushi Kiuchi , Kesami Hagiwara
摘要: A data processor apparatus having first and second instruction storages for holding a series of instructions to be executed reiteratively. The number of instructions is calculated based on the difference between a start address and an end address respectively stored in a start address register and an end address register. When the number of instructions constituting the series of instructions is less than the capacity of the second instruction storage, the series of instructions is read from the second instruction storage and executed. When the number of instructions is greater than the capacity of the second instruction storage, the series of instructions is read from the first instruction storage.
摘要翻译: 一种具有第一和第二指令存储器的数据处理器装置,用于保持要重复执行的一系列指令。 基于分别存储在开始地址寄存器和结束地址寄存器中的开始地址和结束地址之间的差来计算指令数。 当构成一系列指令的指令的数量小于第二指令存储的容量时,从第二指令存储器读取一系列指令并执行。 当指令数量大于第二指令存储器的容量时,从第一指令存储器读取一系列指令。
-
公开(公告)号:US09564805B2
公开(公告)日:2017-02-07
申请号:US14009715
申请日:2012-04-09
申请人: Shinya Sano , Masashi Horiguchi , Takahiro Miki , Mitsuru Hiraki
发明人: Shinya Sano , Masashi Horiguchi , Takahiro Miki , Mitsuru Hiraki
摘要: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
摘要翻译: 其中放大器的偏移对输出电压的影响减小的电压产生电路具有在相同电位的发射极端子的第一和第二双极晶体管(Q1,Q2)。 Q1的基极端子设置在Q2的集电极侧。 第一电阻元件将Q2的集电极侧与Q2的基极侧连接; 并且第二电阻元件(R1)将Q1的集电极侧连接到R2。 第三电阻元件(R3)将Q2的基极端子与发射极端子的电位相连。 放大器(A1)输出基于Q1和Q2的集电极侧之间的电压差的电压; 电压电流转换部(MP1,MP2)将放大器输出转换为R1和R2的连接节点的电流。 然后基于所产生的电流输出电压。
-
公开(公告)号:US08017986B2
公开(公告)日:2011-09-13
申请号:US12718111
申请日:2010-03-05
申请人: Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人: Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号: H01L29/788
CPC分类号: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译: 半导体器件包括多个非易失性存储单元(1)。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分(3)和选择第一晶体管部分的MOS型第二晶体管部分(4)。 第二晶体管部分具有连接到位线的位线电极(16)和连接到控制栅极控制线的控制栅电极(18)。 第一晶体管部分具有连接到源极线的源极线电极(10),连接到存储器栅极控制线的存储栅电极(14)和直接位于存储栅电极下方的电荷存储区域(11)。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc,并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm,它们具有tc
-
公开(公告)号:US20110115461A1
公开(公告)日:2011-05-19
申请号:US12926516
申请日:2010-11-23
申请人: Masashi Horiguchi , Mitsuru Hiraki
发明人: Masashi Horiguchi , Mitsuru Hiraki
IPC分类号: G05F3/02
CPC分类号: G05F3/242 , H01L2224/16145 , H01L2224/32245 , H01L2224/48137 , H01L2224/4826 , H01L2224/73215 , Y10T307/76 , H01L2924/00
摘要: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises, and occurrence of noise is restrained.
摘要翻译: 限制在接通电源时与降压动作相关的电源噪声的发生。 降压单元设置有开关电容器型降压电路和串联调节器型降压电路,降压电路的降压电压输出端子共同连接。 两个降压电路的降压电压输出端子的共同连接使得两者的并联驱动成为可能的两者的选择性驱动,或者是两者的连续驱动。 在连续驱动中,即使在驱动串联调节器型降压电路之后驱动开关电容器型降压电路以向负载提供降压电压,开关电容器类型降压电路仅需要 由于负载而被补偿放电,并且可以将电容器的充电电流的峰值保持为低。 当开关电容器型降压电路的工作开始时,不产生大的冲击电流,并且抑制噪声的发生。
-
公开(公告)号:US07881026B2
公开(公告)日:2011-02-01
申请号:US12606715
申请日:2009-10-27
申请人: Takayasu Ito , Mitsuru Hiraki , Koichi Ashiga
发明人: Takayasu Ito , Mitsuru Hiraki , Koichi Ashiga
IPC分类号: H02H3/22
CPC分类号: H01L23/50 , H01L23/60 , H01L24/06 , H01L27/0207 , H01L27/0266 , H01L2224/05553 , H01L2224/05554 , H01L2924/01029 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H02M3/00 , H02M3/07 , H02M3/157 , H01L2924/00
摘要: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
摘要翻译: 形成在半导体芯片上的集成电路包括用于降低外部提供的电源电压以产生内部电源电压的电压调节器,以及基于内部电源电压工作的内部电路。 电压调节器被放置在缓冲器和保护元件的区域中用于输入/输出信号和电源电压,使得由于电压调节器的片上提供而导致的开销面积被最小化。 内部电源电压通过环形主电源线分配到内部电路,电极焊盘用于连接外部电容器,用于稳定其上提供的内部电源电压,从而内部电源电压稳定,功耗 集成电路最小化。
-
公开(公告)号:US20100109446A1
公开(公告)日:2010-05-06
申请号:US12654718
申请日:2009-12-30
申请人: Masashi Horiguchi , Mitsuru Hiraki
发明人: Masashi Horiguchi , Mitsuru Hiraki
IPC分类号: H02B1/24
CPC分类号: G05F3/242 , H01L2224/16145 , H01L2224/32245 , H01L2224/48137 , H01L2224/4826 , H01L2224/73215 , Y10T307/76 , H01L2924/00
摘要: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises, and occurrence of noise is restrained.
-
公开(公告)号:US07414283B2
公开(公告)日:2008-08-19
申请号:US11415129
申请日:2006-05-02
申请人: Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人: Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号: H01L29/788
CPC分类号: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译: 半导体器件包括多个非易失性存储单元(1)。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分(3)和选择第一晶体管部分的MOS型第二晶体管部分(4)。 第二晶体管部分具有连接到位线的位线电极(16)和连接到控制栅极控制线的控制栅电极(18)。 第一晶体管部分具有连接到源极线的源极线电极(10),连接到存储器栅极控制线的存储栅电极(14)和直接位于存储栅电极下方的电荷存储区域(11)。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc,并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm,它们具有tc
-
公开(公告)号:US07394706B2
公开(公告)日:2008-07-01
申请号:US11717080
申请日:2007-03-13
申请人: Masashi Horiguchi , Mitsuru Hiraki
发明人: Masashi Horiguchi , Mitsuru Hiraki
IPC分类号: G11C7/00
CPC分类号: G11C5/147 , H03K19/0013
摘要: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
摘要翻译: 提供了具有降低的消耗电流的半导体集成电路器件。 第一降压电路固定地形成低于通过外部端子提供的电源电压的内部电压。 根据控制信号,第二降压电路在第一模式和第二模式之间切换。 在第一模式中,内部电压由通过外部端子提供的电源电压形成,并通过第二输出端子输出。 在第二模式中,形成内部电压的控制系统的工作电流被中断,并且建立了输出高阻抗状态。 第一降压电路的第一输出端子和第二降压电路的第二输出端子共同连接,并且内部电压被提供给内部电路。
-
公开(公告)号:US07372245B2
公开(公告)日:2008-05-13
申请号:US11727559
申请日:2007-03-27
CPC分类号: G05F3/222
摘要: A difference between both emitter voltages of a first transistor having an emitter through which a first current flows, and at least one second transistor having an emitter through which such a second current as to reach a current density thereof smaller than that of the emitter of the first transistor flows, is applied across a first resistor. A second resistor is provided between the emitter of the second transistor and a circuit's ground potential. A third resistor and a fourth resistor are respectively provided between collectors of the first and second transistors and a power supply voltage. Such an output voltage that a collector voltage of the first transistor and a collector voltage of the second transistor become equal is formed in response to the collector voltage of the first transistor and the collector voltage of the second transistor and supplied to bases of the first and second transistors in common. A temperature sense voltage is formed from a connecting point of the first and second resistors.
摘要翻译: 具有第一电流流经的发射极的第一晶体管的两个发射极电压和至少一个具有发射极的第二晶体管之间的差异,通过该发射极,这样的第二电流达到其电流密度小于 第一晶体管流过第一电阻器。 第二电阻器设置在第二晶体管的发射极和电路的地电位之间。 分别在第一和第二晶体管的集电极之间设置第三电阻器和第四电阻器,以及电源电压。 响应于第一晶体管的集电极电压和第二晶体管的集电极电压而形成第一晶体管的集电极电压和第二晶体管的集电极电压相等的这种输出电压,并被提供给第一晶体管的基极和 第二个晶体管是共同的。 温度感测电压由第一和第二电阻器的连接点形成。
-
-
-
-
-
-
-
-
-