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    Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device
    12.
    发明申请
    Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device 审中-公开
    多层布线结构，掩埋布线的形成方法，半导体器件，半导体器件的制造方法，半导体安装器件以及制造半导体安装器件的方法

    公开(公告)号：US20050170641A1

    公开(公告)日：2005-08-04

    申请号：US11014883

    申请日：2004-12-20

    申请人： Seiichi Kondo ,  Kaori Misawa

    发明人： Seiichi Kondo ,  Kaori Misawa

    IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

    CPC分类号： H01L21/7684 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a buried wiring in a low-k dielectric film, includes: forming a low-k dielectric film having a dielectric constant of 3 or less on an underlayer; removing the low-k dielectric film by a first width from an edge of the underlayer; forming a cap film on the low-k dielectric film, after removing the low-k dielectric film by the first width; forming a groove in the cap film and the low-k dielectric film; forming a conductive film in the groove and on the cap film; removing the conductive film by a second width, different from the first width by 1 mm or more, from the edge of the underlayer; and polishing unnecessary portions of the conductive film on the cap film, after removing the conductive film by the second width.

    摘要翻译： 在低k电介质膜中形成掩埋布线的方法包括：在底层上形成介电常数为3以下的低k电介质膜; 从底层的边缘去除第一宽度的低k电介质膜; 在将低k电介质膜除去第一宽度之后，在低k电介质膜上形成盖膜; 在盖膜和低k电介质膜中形成凹槽; 在槽和盖膜中形成导电膜; 从所述底层的边缘除去所述导电膜的距离不同于所述第一宽度1mm以上的第二宽度; 并且在将导电膜除去第二宽度之后，在盖膜上抛光导电膜的不需要的部分。

    Method for manufacturing a semiconductor device
    16.
    发明授权
    Method for manufacturing a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US06326299B1

    公开(公告)日：2001-12-04

    申请号：US09361989

    申请日：1999-07-28

    申请人： Yoshio Homma ,  Seiichi Kondo ,  Noriyuki Sakuma ,  Naofumi Ohashi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada

    发明人： Yoshio Homma ,  Seiichi Kondo ,  Noriyuki Sakuma ,  Naofumi Ohashi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada

    IPC分类号： H01L214763

    CPC分类号： H01L21/3212 ,  C09G1/02 ,  H01L21/7684

    摘要： In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

    摘要翻译： 为了抑制在绝缘膜中形成的槽中以镶嵌法形成铜基合金镶嵌布线时在抛光期间在铜基合金层上发生的凹陷等的增加，下金属层的研磨速度 设定为比其蚀刻速度快五倍以上，并且当上金属层13成为布线时，绝缘膜的抛光速率被设定为低于下金属层的抛光速率，下金属层 12成为屏障分别抛光。 因此，对象镶嵌布线可以分别形成在绝缘层和每个金属层上的凹陷上较少的侵蚀。

    Service providing system, service providing method, and information processing apparatus
    17.
    发明授权
    Service providing system, service providing method, and information processing apparatus 有权

    公开(公告)号：US10243924B2

    公开(公告)日：2019-03-26

    申请号：US15228085

    申请日：2016-08-04

    申请人： Hiroki Ohzaki ,  Yasuharu Fukuda ,  Seiichi Kondo

    发明人： Hiroki Ohzaki ,  Yasuharu Fukuda ,  Seiichi Kondo

    IPC分类号： G06F7/10 ,  H04L29/06 ,  G07F7/10

    摘要： A service providing system includes an application configured to provide a service to a terminal device that has made a service request including use identification information; a creator configured to create group identification information for identifying a group of the use identification information, based on a creation request from the application; an issuer configured to issue the use identification information associated with the group identification information, based on an issue request from the application, the issue request including the group identification information; and a verifier configured to verify the use identification information, based on a verification request from the application, the verification request including the group identification information and the use identification information. The application includes a verification requester configured to send the verification request to the verifier; and a process executor configured to execute a process in response to the service request, when the verification result is successful.

    Process for manufacturing semiconductor integrated circuit device
    18.
    发明授权
    Process for manufacturing semiconductor integrated circuit device 有权
    半导体集成电路器件制造工艺

    公开(公告)号：US08129275B2

    公开(公告)日：2012-03-06

    申请号：US12700784

    申请日：2010-02-05

    申请人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

    发明人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

    IPC分类号： H01L21/44

    CPC分类号： H01L21/0209 ,  G09G5/399 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

    摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

    摘要翻译： 为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层 含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

    PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    19.
    发明申请
    PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    制造半导体集成电路器件的工艺

    公开(公告)号：US20100136786A1

    公开(公告)日：2010-06-03

    申请号：US12700784

    申请日：2010-02-05

    申请人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

    发明人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

    IPC分类号： H01L21/768

    CPC分类号： H01L21/0209 ,  G09G5/399 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

    摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

    摘要翻译： 为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层 含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

    Polishing method
    20.
    发明授权
    Polishing method 有权
    抛光方法

    公开(公告)号：US07132367B2

    公开(公告)日：2006-11-07

    申请号：US10441063

    申请日：2003-05-20

    申请人： Seiichi Kondo ,  Yoshio Homma ,  Noriyuki Sakuma ,  Kenichi Takeda ,  Kenji Hinode

    发明人： Seiichi Kondo ,  Yoshio Homma ,  Noriyuki Sakuma ,  Kenichi Takeda ,  Kenji Hinode

    IPC分类号： H01L21/302

    CPC分类号： C23F3/06 ,  B24B37/04 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/7684

    摘要： A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

    摘要翻译： 抑制了划痕，剥离，凹陷和侵蚀的抛光技术，不需要复杂的清洁处理和浆料供应/处理设备，并且消耗品如浆料和抛光垫的成本降低。在绝缘膜上形成的金属膜 包括用包含氧化剂的抛光溶液和使氧化物水溶性但不含抛光磨料的物质抛光的凹槽。