公开(公告)号：US20050073004A1

公开(公告)日：2005-04-07

申请号：US10929727

申请日：2004-08-31

Applicant: Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

Inventor： Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

IPC: H01L29/06 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/7811 ,  H01L29/407 ,  H01L29/7813 ,  Y10S257/908

Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Abstract translation: 常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。 因此，由于周边地区的面积大，元素区域的增加受到限制。 因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。 用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。 由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。 此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

公开(公告)号：US07825474B2

公开(公告)日：2010-11-02

申请号：US11860206

申请日：2007-09-24

Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

IPC: H01L23/62 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7804 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，在设置在操作区域的外周的导电层中形成保护二极管。

公开(公告)号：US20100163922A1

公开(公告)日：2010-07-01

申请号：US12645942

申请日：2009-12-23

Applicant: Shuji Yoneda ,  Hiroyasu Ishida ,  Makoto Oikawa

Inventor： Shuji Yoneda ,  Hiroyasu Ishida ,  Makoto Oikawa

IPC: H01L27/06

CPC classification number: H01L27/0652 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/866 ,  H03K17/163

Abstract: By integrating a diode and a resistor connected in parallel into the same chip as an IGBT and connecting a cathode of the diode to a gate of the IGBT, the value of dv/dt can be limited to a predetermined range inside the chip of the IGBT without a deterioration in turn-on characteristics. Since the chip includes a resistor having such a resistance that a dv/dt breakdown of the IGBT can be prevented, the IGBT can be prevented from being broken by an increase in dv/dt at a site (user site) to which the chip is supplied.

Abstract translation: 通过将二极管和电阻并联连接到与IGBT相同的芯片上并将二极管的阴极连接到IGBT的栅极，dv / dt的值可以限制在IGBT的芯片内部的预定范围内 没有导通特性的恶化。 由于芯片包括具有能够防止IGBT的dv / dt击穿的电阻的电阻器，因此可以防止IGBT在芯片的场所（用户现场）处的dv / dt增加而被破坏 提供。

公开(公告)号：US07692240B2

公开(公告)日：2010-04-06

申请号：US11797900

申请日：2007-05-08

Applicant: Hiroyasu Ishida ,  Yasunari Noguchi

Inventor： Hiroyasu Ishida ,  Yasunari Noguchi

IPC: H01L29/94

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad electrode, are kept at a predetermined potential. Thus, a predetermined drain-source reverse breakdown voltage can be secured without providing a p+ type impurity region on the entire surface below the gate pad electrode.

Abstract translation: 通道区域和栅电极也与栅极焊盘电极下面的晶体管单元连续地设置。 晶体管单元形成为条状图案并允许与源极接触。 以这种方式，位于栅极焊盘电极下方的沟道区域和栅极电极保持在预定电位。 因此，可以确保在栅极电极下方的整个表面上不设置p +型杂质区域的预定的漏极 - 反向击穿电压。

公开(公告)号：US07230300B2

公开(公告)日：2007-06-12

申请号：US10929727

申请日：2004-08-31

Applicant: Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

Inventor： Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7811 ,  H01L29/407 ,  H01L29/7813 ,  Y10S257/908

Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Abstract translation: 常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。 因此，由于周边地区的面积大，元素区域的增加受到限制。 因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。 用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。 由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。 此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

公开(公告)号：US20060180836A1

公开(公告)日：2006-08-17

申请号：US11355196

申请日：2006-02-16

Applicant: Hiroyasu Ishida ,  Makoto Oikawa ,  Kikuo Okada ,  Shouji Miyahara ,  Naohiro Ochiai ,  Kazunari Kushiyama

Inventor： Hiroyasu Ishida ,  Makoto Oikawa ,  Kikuo Okada ,  Shouji Miyahara ,  Naohiro Ochiai ,  Kazunari Kushiyama

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7813

Abstract: In the present invention, in a pattern in which gate electrodes are provided in a stripe shape and source regions are provided in a ladder shape, body regions are provided in a stripe shape parallel to the gate electrodes. A first body region is exposed to a surface of a channel layer between first source regions adjacent to the gate electrode, and a second body region is provided below a second source region which connects the first source regions to each other. Thus, avalanche resistance can be improved. Moreover, since a mask for forming the body region is no longer required, there is a margin in accuracy of alignment.

Abstract translation: 在本发明中，在栅电极呈条状而源极区设置为梯状的图案中，以与栅电极平行的条状形成体区。 第一体区域暴露于与栅电极相邻的第一源极区域之间的沟道层的表面，并且第二体区域设置在将第一源极区域彼此连接的第二源极区域的下方。 因此，可以提高雪崩阻力。 此外，由于不再需要用于形成身体区域的掩模，所以对准精度有余量。

公开(公告)号：US08344457B2

公开(公告)日：2013-01-01

申请号：US12711647

申请日：2010-02-24

Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

IPC: H01L23/62 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7804 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，在设置在操作区域的外周的导电层中形成保护二极管。

公开(公告)号：US07439137B2

公开(公告)日：2008-10-21

申请号：US11123248

申请日：2005-05-06

Applicant: Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

Inventor： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/3003 ,  H01L21/76886 ,  H01L21/823487 ,  H01L29/456

Abstract: In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

Abstract translation: 在MOSFET中，在形成元件区之后，在阻挡金属层的后面形成布线层，进行氢退火。 然而，在n沟道MOSFET的情况下，由于阻挡金属层的遮挡特性，阈值电压降低。 因此，通道层中杂质浓度的增加引起导通电阻的降低被抑制的问题。 根据本发明，在形成阻挡金属层之后，在层间绝缘膜上的阻挡金属层中设置开口，在形成布线层之后进行氢退火处理。 因此，到达基板的氢的量进一步增加，并且抑制了阈值电压的降低。 此外，由于可以降低沟道层中的杂质浓度，所以导通电阻降低。

公开(公告)号：US20070007588A1

公开(公告)日：2007-01-11

申请号：US11471733

申请日：2006-06-21

Applicant: Hiroyasu Ishida ,  Tadao Mandai ,  Atsuya Ushida ,  Hiroaki Saito

Inventor： Hiroyasu Ishida ,  Tadao Mandai ,  Atsuya Ushida ,  Hiroaki Saito

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/66734

Abstract: A first electrode layer, which comes into contact with a source region, and a second electrode layer, which comes into contact with a body (back gate) region, are provided. The first and second electrode layers are insulated from each other and are extended in a direction different from an extending direction of a trench. It is possible to individually apply potentials to the first and second electrode layers, and to perform control for preventing a reverse current caused by a parasitic diode. Therefore, a bidirectional switching element can be realized by use of one MOSFET.

Abstract translation: 设置与源极区域接触的第一电极层和与主体（背栅极）区域接触的第二电极层。 第一和第二电极层彼此绝缘并且沿与沟槽的延伸方向不同的方向延伸。 可以分别对第一和第二电极层施加电位，并且执行用于防止由寄生二极管引起的反向电流的控制。 因此，可以通过使用一个MOSFET来实现双向开关元件。

公开(公告)号：US07732869B2

公开(公告)日：2010-06-08

申请号：US11860689

申请日：2007-09-25

Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

IPC: H01L23/62

CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，保护二极管形成在栅极电极下方具有条纹形状的多晶硅中。