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    Insulated-gate semiconductor device and PN junction diodes
    1.
    发明授权
    Insulated-gate semiconductor device and PN junction diodes 有权
    绝缘栅半导体器件和PN结二极管

    公开(公告)号：US07825474B2

    公开(公告)日：2010-11-02

    申请号：US11860206

    申请日：2007-09-24

    Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    IPC: H01L23/62 ,  H01L29/66

    CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7804 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

    Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，在设置在操作区域的外周的导电层中形成保护二极管。

    Insulated gate semiconductor device
    2.
    发明授权
    Insulated gate semiconductor device 有权
    绝缘栅半导体器件

    公开(公告)号：US07692240B2

    公开(公告)日：2010-04-06

    申请号：US11797900

    申请日：2007-05-08

    Applicant: Hiroyasu Ishida ,  Yasunari Noguchi

    Inventor： Hiroyasu Ishida ,  Yasunari Noguchi

    IPC: H01L29/94

    CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

    Abstract: Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad electrode, are kept at a predetermined potential. Thus, a predetermined drain-source reverse breakdown voltage can be secured without providing a p+ type impurity region on the entire surface below the gate pad electrode.

    Abstract translation: 通道区域和栅电极也与栅极焊盘电极下面的晶体管单元连续地设置。 晶体管单元形成为条状图案并允许与源极接触。 以这种方式，位于栅极焊盘电极下方的沟道区域和栅极电极保持在预定电位。 因此，可以确保在栅极电极下方的整个表面上不设置p +型杂质区域的预定的漏极 - 反向击穿电压。

    Insulated-gate semiconductor device with protection diode
    3.
    发明授权
    Insulated-gate semiconductor device with protection diode 有权
    带保护二极管的绝缘栅半导体器件

    公开(公告)号：US08344457B2

    公开(公告)日：2013-01-01

    申请号：US12711647

    申请日：2010-02-24

    Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    IPC: H01L23/62 ,  H01L29/66

    CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7804 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

    Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，在设置在操作区域的外周的导电层中形成保护二极管。

    Insulated-gate semiconductor device
    4.
    发明授权
    Insulated-gate semiconductor device 有权
    绝缘栅半导体器件

    公开(公告)号：US07732869B2

    公开(公告)日：2010-06-08

    申请号：US11860689

    申请日：2007-09-25

    Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    IPC: H01L23/62

    CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

    Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，保护二极管形成在栅极电极下方具有条纹形状的多晶硅中。

    INSULATED-GATE SEMICONDUCTOR DEVICE
    5.
    发明申请
    INSULATED-GATE SEMICONDUCTOR DEVICE 有权
    绝缘栅半导体器件

    公开(公告)号：US20080079079A1

    公开(公告)日：2008-04-03

    申请号：US11860689

    申请日：2007-09-25

    Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    IPC: H01L27/06

    CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

    Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，保护二极管形成在栅极电极下方具有条纹形状的多晶硅中。

    Insulated gate semiconductor device
    6.
    发明申请
    Insulated gate semiconductor device 有权
    绝缘栅半导体器件

    公开(公告)号：US20070262390A1

    公开(公告)日：2007-11-15

    申请号：US11797900

    申请日：2007-05-08

    Applicant: Hiroyasu Ishida ,  Yasunari Noguchi

    Inventor： Hiroyasu Ishida ,  Yasunari Noguchi

    IPC: H01L29/94

    CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

    Abstract: Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad electrode, are kept at a predetermined potential. Thus, a predetermined drain-source reverse breakdown voltage can be secured without providing a p+ type impurity region on the entire surface below the gate pad electrode.

    Abstract translation: 通道区域和栅电极也与栅极焊盘电极下面的晶体管单元连续地设置。 晶体管单元形成为条状图案并允许与源极接触。 以这种方式，位于栅极焊盘电极下方的沟道区域和栅极电极保持在预定电位。 因此，可以确保在栅极焊盘电极下方的整个表面上不提供p + +型杂质区域的预定漏极 - 源极反向击穿电压。

    Method of processing semiconductor wafer
    7.
    发明授权
    Method of processing semiconductor wafer 有权
    半导体晶片的处理方法

    公开(公告)号：US07902053B2

    公开(公告)日：2011-03-08

    申请号：US12199547

    申请日：2008-08-27

    Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama

    Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama

    IPC: H01L21/20

    CPC classification number: H01L29/0634 ,  H01L21/26586

    Abstract: Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.

    Abstract translation: n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻在半导体衬底上交替进行至少三次以形成外延层的所有半导体层。 因此，半导体层的杂质浓度分布可以是均匀的，并且pn结可以垂直于晶片表面形成。 此外，半导体层各自可以形成为窄的宽度，使得其杂质浓度增加。 利用这种结构，可以实现高击穿电压和低电阻。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07777316B2

    公开(公告)日：2010-08-17

    申请号：US12239368

    申请日：2008-09-26

    Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama ,  Tetsuya Okada

    Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama ,  Tetsuya Okada

    IPC: H01L23/02 ,  H01L23/34

    CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.

    Abstract translation: 提供一种半导体器件，其中在具有超结结构的半导体区域的端部中设置围绕元件区域的绝缘区域。 由于元件区域中的耗尽层在绝缘区域中结束，元件区域的端部不形成为曲面形状。 换句话说，耗尽层没有内部电场集中的曲面。 因此，通过证明终端区域，不需要采取措施使耗尽层在水平方向上扩展。 由于不需要端子区域，因此可以减小芯片尺寸。 或者，可以扩展元件区域的区域。

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