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    Synchronous semiconductor memory device
    11.
    发明授权
    Synchronous semiconductor memory device 失效
    同步半导体存储器件

    公开(公告)号：US5384745A

    公开(公告)日：1995-01-24

    申请号：US46333

    申请日：1993-04-14

    申请人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

    发明人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

    IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

    摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

    摘要翻译： 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止对所需位的写入，如果数据写入应当是数据写入时，可以将数据集中写入所选存储单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。

    SEMICONDUCTOR DEVICE INCLUDING MEMORY CAPABLE OF REDUCING POWER CONSUMPTION
    12.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING MEMORY CAPABLE OF REDUCING POWER CONSUMPTION 有权
    半导体器件，包括可减少功耗的存储器

    公开(公告)号：US20130039134A1

    公开(公告)日：2013-02-14

    申请号：US13566779

    申请日：2012-08-03

    申请人： Hisashi Iwamoto ,  Yuji Yano ,  Kazunari Inoue

    发明人： Hisashi Iwamoto ,  Yuji Yano ,  Kazunari Inoue

    IPC分类号： G11C7/22

    CPC分类号： G11C7/1069 ,  G11C7/1006 ,  G11C7/1096 ,  G11C7/222

    摘要： A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

    摘要翻译： 半导体器件包括多个存储器阵列和多个存储器阵列控制电路。 多个存储器阵列控制电路中的每一个包括用于控制存储器阵列的读/写操作的读/写控制电路，以及用于基于时钟信号和来自该存储器阵列控制电路的输出信号选择和激活存储器阵列的选择电路 读/写控制电路。

    Semiconductor device allowing easy confirmation of operation of built in clock generation circuit
    13.
    发明授权
    Semiconductor device allowing easy confirmation of operation of built in clock generation circuit 失效
    半导体器件允许容易地确认内置时钟发生电路的操作

    公开(公告)号：US06763079B1

    公开(公告)日：2004-07-13

    申请号：US09252910

    申请日：1999-02-19

    申请人： Hisashi Iwamoto

    发明人： Hisashi Iwamoto

    IPC分类号： H04L708

    CPC分类号： G11C29/12015 ,  G01R31/31725 ,  G01R31/31727 ,  G11C29/02 ,  G11C29/50012 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00241 ,  H03L7/0814 ,  H03L7/089

    摘要： A shift register which outputs a delay control signal for a delay line is made controllable at a test mode by a TEST MODE address buffer receiving an external address as a control signal and a phase comparator. Thus whether the delay of the delay line is correctly controlled or not can be confirmed through observation of an internal clock signal int. CLK output from an output buffer at the test and an external clock signal ext. CLK.

    摘要翻译： 输出用于延迟线的延迟控制信号的移位寄存器通过接收作为控制信号的外部地址的TEST MODE地址缓冲器和相位比较器在测试模式下被控制。 因此，可以通过观察内部时钟信号int来确认延迟线的延迟是否被正确控制。 来自测试时的输出缓冲器的CLK输出和外部时钟信号分频。 CLK。

    Semiconductor device outputting data at a timing with reduced jitter
    14.
    发明授权
    Semiconductor device outputting data at a timing with reduced jitter 失效
    半导体器件在抖动减小的定时输出数据

    公开(公告)号：US06741507B2

    公开(公告)日：2004-05-25

    申请号：US10224343

    申请日：2002-08-21

    申请人： Hisashi Iwamoto

    发明人： Hisashi Iwamoto

    IPC分类号： G11C700

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/222

    摘要： In a DLL circuit between a phase comparator and a digital filter there is provided a signal switching portion preventing control signals UP and DOWN from being transmitted after a clock enable signal extCKE is activated and before a predetermined period of time elapses. Thus after a semiconductor device returns from a power down mode and before a predetermined period of time elapses it continues to stop updating an amount of delay of a delay line. Thus before an internal power supply potential stabilizes the delay line does not have a varying amount of delay and as a result the semiconductor device can output data at a timing free of significant fluctuation.

    摘要翻译： 在相位比较器和数字滤波器之间的DLL电路中，提供了一个信号切换部分，该信号切换部分防止在时钟使能信号extCKE被激活之后并在经过预定时间段之前传输控制信号UP和DOWN。 因此，在半导体器件从断电模式返回并且在经过预定时间段之前，它继续停止更新延迟线的延迟量。 因此，在内部电源电位稳定之前，延迟线不具有变化的延迟量，因此半导体器件可以在没有显着波动的时刻输出数据。

    Semiconductor device with clock generation circuit
    15.
    发明授权
    Semiconductor device with clock generation circuit 失效
    具有时钟发生电路的半导体器件

    公开(公告)号：US06720807B1

    公开(公告)日：2004-04-13

    申请号：US10377738

    申请日：2003-03-04

    申请人： Takashi Kubo ,  Hisashi Iwamoto

    发明人： Takashi Kubo ,  Hisashi Iwamoto

    IPC分类号： H03L700

    CPC分类号： H03K19/0005 ,  G06F1/10 ,  H03L7/0812

    摘要： An impedance adjustment circuit generates an internal impedance adjustment signal and an impedance adjustment entry signal based on an externally applied impedance control signal. A data processing circuit decodes the internal impedance adjustment signal in synchronization with an internal clock signal to generate an output buffer drive signal of 5 bits. When the output buffer drive signal is applied to an output circuit of the succeeding stage as well as to an output replica circuit in a DLL circuit, the impedance of the output replica circuit is adjusted following adjustment of the output impedance.

    摘要翻译： 阻抗调整电路根据外部施加的阻抗控制信号产生内部阻抗调整信号和阻抗调整输入信号。 数据处理电路与内部时钟信号同步地解码内部阻抗调整信号，以产生5位的输出缓冲器驱动信号。 当输出缓冲器驱动信号被施加到后级的输出电路以及DLL电路中的输出复制电路时，在调节输出阻抗之后调整输出复制电路的阻抗。

    Synchronous semiconductor memory device and synchronous memory module
    16.
    发明授权
    Synchronous semiconductor memory device and synchronous memory module 失效
    同步半导体存储器件和同步存储器模块

    公开(公告)号：US5815462A

    公开(公告)日：1998-09-29

    申请号：US800905

    申请日：1997-02-12

    申请人： Yasuhiro Konishi ,  Hisashi Iwamoto ,  Takashi Araki ,  Yasumitsu Murai ,  Seiji Sawada

    发明人： Yasuhiro Konishi ,  Hisashi Iwamoto ,  Takashi Araki ,  Yasumitsu Murai ,  Seiji Sawada

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/225 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/22

    摘要： A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

    摘要翻译： 用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。 可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。 内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过 输出缓冲区。 提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。

    Synchronous semiconductor memory device
    17.
    发明授权
    Synchronous semiconductor memory device 失效
    同步半导体存储器件

    公开(公告)号：US5796669A

    公开(公告)日：1998-08-18

    申请号：US900123

    申请日：1997-07-25

    申请人： Takashi Araki ,  Hisashi Iwamoto ,  Yasuhiro Konishi

    发明人： Takashi Araki ,  Hisashi Iwamoto ,  Yasuhiro Konishi

    IPC分类号： G11C11/407 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C7/1063

    摘要： Switches (11, 12) select either of refresh address counters (6a, 6b) in accordance with a refresh bank set signal (.phi.REFADD) when a bank refresh signal (.phi.BANKREF) is activated. An internal bank address (int.BA) serves as the refresh bank set signal (.phi.REFADD) to control the switch (12) and the refresh address counter (6a or 6b) designated by the internal bank address (int.BA) performs a count operation in synchronization with a refresh clock (.phi.REFCLK). The switch (11) outputs either of refresh addresses (Ref.Add.sub.-- A , Ref.Add.sub.-- B ) which is updated. With this configuration provided is an SDRAM which allows access to data during a refresh operation.

    摘要翻译： 当bank刷新信号（phi BANKREF）被激活时，开关（11,12）根据刷新组设置信号（phi REFADD）来选择刷新地址计数器（6a，6b）。 内部银行地址（int.BA）用作刷新组设置信号（phi REFADD）以控制开关（12），由内部银行地址（int.BA）指定的刷新地址计数器（6a或6b）执行 计数操作与刷新时钟同步（phi REFCLK）。 开关（11）输出更新的刷新地址（Ref.Add-A <0:10>，Ref.Add-B <0:10>）。 提供这种配置是允许在刷新操作期间访问数据的SDRAM。