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154 条记录 (耗时 0.038 秒)

    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same
    12.
    发明申请
    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
    具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法

    公开(公告)号：US20080036006A1

    公开(公告)日：2008-02-14

    申请号：US11802281

    申请日：2007-05-22

    申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

    摘要翻译： 具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。 该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。 在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

    Nonaqueous electrolyte for improving performance and litium secondary battery comprising the same
    13.
    发明申请
    Nonaqueous electrolyte for improving performance and litium secondary battery comprising the same 有权
    用于改善性能的非水电解质和包含其的二次电池

    公开(公告)号：US20070059606A1

    公开(公告)日：2007-03-15

    申请号：US11521892

    申请日：2006-09-15

    申请人： Ho Lee ,  Tae Park ,  Yong Choi ,  Soo Yoon ,  Hong Park ,  Hyun Jung ,  Jeong Ahn

    发明人： Ho Lee ,  Tae Park ,  Yong Choi ,  Soo Yoon ,  Hong Park ,  Hyun Jung ,  Jeong Ahn

    IPC分类号： H01M10/40

    CPC分类号： H01M10/0567 ,  H01M4/131 ,  H01M4/139 ,  H01M10/04 ,  H01M10/052

    摘要： Disclosed is a lithium secondary battery comprising a cathode, an anode, an electrolyte and a separator, wherein the anode comprises an anode active material having a specific surface area of 3 m2/g or less, and the electrolyte comprises 0.1˜6 parts by weight of a propane sultone-based compound based on 100 parts by weight of the electrolyte. The lithium secondary battery solves the problem of performance degradation caused by the use of an increased amount of a propane sultone-based compound required to form a SEI film on the surface of an anode upon the first charge cycle. Also, the lithium secondary battery can provide improved cycle characteristics and high-temperature storage characteristics.

    摘要翻译： 公开了一种包括阴极，阳极，电解质和隔膜的锂二次电池，其中阳极包括比表面积为3m 2 / g以下的负极活性物质， 基于100重量份的电解质，电解质包含0.1〜6重量份的丙烷磺内酯类化合物。 锂二次电池解决了在第一次充电循环时在阳极表面上使用增加量的形成SEI膜所需的丙烷磺内酯类化合物引起的性能下降的问题。 此外，锂二次电池可以提供改进的循环特性和高温存储特性。

    Additive for nonaqueous electrolyte and secondary battery using the same
    15.
    发明申请
    Additive for nonaqueous electrolyte and secondary battery using the same 有权
    用于非水电解质和使用其的二次电池的添加剂

    公开(公告)号：US20070015062A1

    公开(公告)日：2007-01-18

    申请号：US11479305

    申请日：2006-06-30

    申请人： Ho Lee ,  Tae Park ,  Yong Choi ,  Hong Park

    发明人： Ho Lee ,  Tae Park ,  Yong Choi ,  Hong Park

    IPC分类号： H01M10/40 ,  H01M2/16

    CPC分类号： H01M10/0567 ,  H01M4/13 ,  H01M4/137 ,  H01M4/60 ,  H01M10/052 ,  H01M10/0568 ,  H01M10/0569 ,  H01M2004/027 ,  Y02T10/7011

    摘要： Disclosed is an electrolyte for a battery, which comprises: (a) an electrolyte salt; (b) a solvent for electrolyte; and (c) a compound represented by the following formula 1: wherein R is a halogen atom, or a halogen-substituted or non-substituted C1˜C10 alkyl group or alkenyl group. An electrode comprising a passivation layer partially or totally formed on a surface thereof, wherein the passivation layer comprises a compound represented by the following Formula 1 or a chemical reaction product thereof, and a secondary battery using the electrolyte and/or the electrode are also disclosed. The compound can improve the initial charge/discharge efficiency and cycle life characteristics of a secondary battery, and can inhibit a battery from swelling under high-temperature storage conditions.

    摘要翻译： 公开了一种电池用电解质，其包括：（a）电解质盐; （b）电解质溶剂; 和（c）由下式1表示的化合物：其中R是卤素原子，或卤素取代或未取代的C1〜C10烷基或烯基。 一种电极，包括部分或全部形成在其表面上的钝化层，其中钝化层包括由下式1表示的化合物或其化学反应产物，并且还公开了使用电解质和/或电极的二次电池 。 该化合物可以提高二次电池的初始充电/放电效率和循环寿命特性，并且可以抑制电池在高温储存条件下膨胀。

    CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
    16.
    发明申请
    CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
    具有升高的源极和漏极区域的CMOS半导体器件及其制造方法

    公开(公告)号：US20060131656A1

    公开(公告)日：2006-06-22

    申请号：US11285978

    申请日：2005-11-23

    申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7834 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

    摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.

    摘要翻译： 提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。 第一和第二栅极图案分别设置成跨越第一和第二有源区域。 第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。 第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。 在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。 设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。 还提供了制造CMOS器件的方法。

    Methods of fabricating a semiconductor device using a selective epitaxial growth technique
    17.
    发明申请
    Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
    使用选择性外延生长技术制造半导体器件的方法

    公开(公告)号：US20060088968A1

    公开(公告)日：2006-04-27

    申请号：US11299447

    申请日：2005-12-08

    申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.

    摘要翻译： 使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。 将具有凹部的基板装入反应室。 将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。 选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

    Method of forming MOS transistor having fully silicided metal gate electrode
    19.
    发明申请
    Method of forming MOS transistor having fully silicided metal gate electrode 有权

    公开(公告)号：US20060008961A1

    公开(公告)日：2006-01-12

    申请号：US11158978

    申请日：2005-06-22

    申请人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

    发明人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.