公开(公告)号：US20070059606A1

公开(公告)日：2007-03-15

申请号：US11521892

申请日：2006-09-15

申请人： Ho Lee ,  Tae Park ,  Yong Choi ,  Soo Yoon ,  Hong Park ,  Hyun Jung ,  Jeong Ahn

发明人： Ho Lee ,  Tae Park ,  Yong Choi ,  Soo Yoon ,  Hong Park ,  Hyun Jung ,  Jeong Ahn

IPC分类号： H01M10/40

CPC分类号： H01M10/0567 ,  H01M4/131 ,  H01M4/139 ,  H01M10/04 ,  H01M10/052

摘要： Disclosed is a lithium secondary battery comprising a cathode, an anode, an electrolyte and a separator, wherein the anode comprises an anode active material having a specific surface area of 3 m2/g or less, and the electrolyte comprises 0.1˜6 parts by weight of a propane sultone-based compound based on 100 parts by weight of the electrolyte. The lithium secondary battery solves the problem of performance degradation caused by the use of an increased amount of a propane sultone-based compound required to form a SEI film on the surface of an anode upon the first charge cycle. Also, the lithium secondary battery can provide improved cycle characteristics and high-temperature storage characteristics.

摘要翻译： 公开了一种包括阴极，阳极，电解质和隔膜的锂二次电池，其中阳极包括比表面积为3m 2 / g以下的负极活性物质， 基于100重量份的电解质，电解质包含0.1〜6重量份的丙烷磺内酯类化合物。 锂二次电池解决了在第一次充电循环时在阳极表面上使用增加量的形成SEI膜所需的丙烷磺内酯类化合物引起的性能下降的问题。 此外，锂二次电池可以提供改进的循环特性和高温存储特性。

公开(公告)号：US20070015062A1

公开(公告)日：2007-01-18

申请号：US11479305

申请日：2006-06-30

申请人： Ho Lee ,  Tae Park ,  Yong Choi ,  Hong Park

发明人： Ho Lee ,  Tae Park ,  Yong Choi ,  Hong Park

IPC分类号： H01M10/40 ,  H01M2/16

CPC分类号： H01M10/0567 ,  H01M4/13 ,  H01M4/137 ,  H01M4/60 ,  H01M10/052 ,  H01M10/0568 ,  H01M10/0569 ,  H01M2004/027 ,  Y02T10/7011

摘要： Disclosed is an electrolyte for a battery, which comprises: (a) an electrolyte salt; (b) a solvent for electrolyte; and (c) a compound represented by the following formula 1: wherein R is a halogen atom, or a halogen-substituted or non-substituted C1˜C10 alkyl group or alkenyl group. An electrode comprising a passivation layer partially or totally formed on a surface thereof, wherein the passivation layer comprises a compound represented by the following Formula 1 or a chemical reaction product thereof, and a secondary battery using the electrolyte and/or the electrode are also disclosed. The compound can improve the initial charge/discharge efficiency and cycle life characteristics of a secondary battery, and can inhibit a battery from swelling under high-temperature storage conditions.

摘要翻译： 公开了一种电池用电解质，其包括：（a）电解质盐; （b）电解质溶剂; 和（c）由下式1表示的化合物：其中R是卤素原子，或卤素取代或未取代的C1〜C10烷基或烯基。 一种电极，包括部分或全部形成在其表面上的钝化层，其中钝化层包括由下式1表示的化合物或其化学反应产物，并且还公开了使用电解质和/或电极的二次电池 。 该化合物可以提高二次电池的初始充电/放电效率和循环寿命特性，并且可以抑制电池在高温储存条件下膨胀。

公开(公告)号：US20070059588A1

公开(公告)日：2007-03-15

申请号：US11521780

申请日：2006-09-15

申请人： Ho Lee ,  Tae Park ,  Yong Choi ,  Soo Yoon ,  Hong Park

发明人： Ho Lee ,  Tae Park ,  Yong Choi ,  Soo Yoon ,  Hong Park

IPC分类号： H01M2/00

CPC分类号： H01M10/0567 ,  H01M4/131 ,  H01M4/62 ,  H01M10/052 ,  H01M2300/0025 ,  Y02T10/7011

摘要： Disclosed is an electrolyte for batteries, which comprises: (a) an electrolyte salt; (b) an electrolyte solvent; and (c) a sulfonate-based compound containing at least one electron withdrawing group (EWG) selected from the group consisting of a cyano group (—CN), an isocyanate group (—NCO), a thiocyanate group (—SCN) and an isothiocyanate group (—NCS). An electrode comprising the sulfonate-based compound or a chemical reaction product thereof, partially or totally formed on the surface thereof, and an electrochemical device comprising the electrolyte and/or the electrode are also disclosed. The electrochemical device using the sulfonate-based compound containing a cyano group, an isocyanate group, a thiocyanate group and/or an isothiocyanate group as an additive for electrolytes can provide significantly improved high-temperature lifespan characteristics.

摘要翻译： 公开了一种电池用电解质，其包括：（a）电解质盐; （b）电解质溶剂; 和（c）含有至少一个选自氰基（-CN），异氰酸酯基（-NCO），硫氰酸酯基（-SCN）和 - 氰基）的吸电子基团（EWG）的磺酸酯基化合物和 异硫氰酸酯基团（-NCS）。 还公开了包含部分或全部形成在其表面上的磺酸盐基化合物或其化学反应产物的电极和包含电解质和/或电极的电化学装置。 使用含有氰基，异氰酸酯基，硫氰酸酯基和/或异硫氰酸酯基作为电解质添加剂的磺酸基类化合物的电化学装置可以显着提高高温寿命特性。

公开(公告)号：US20080079086A1

公开(公告)日：2008-04-03

申请号：US11831069

申请日：2007-07-31

申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ho Lee ,  Ha-jin Lim

发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ho Lee ,  Ha-jin Lim

IPC分类号： H01L21/336 ,  H01L27/085

CPC分类号： H01L21/823807

摘要： A semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device includes a semiconductor substrate in which PMOS transistor regions and NMOS transistor regions are formed, a PMOS transistor including P-type source and drain regions and a gate electrode, and an NMOS transistor formed on an Si channel region between N-type source and drain regions. The PMOS transistor is formed in each PMOS transistor region, and the gate electrode is formed on a high-dielectric gate insulating film formed on an SiGe channel region between the P-type source and drain regions. Further, the NMOS transistor includes a high-dielectric gate insulating film and a gate electrode formed on the gate insulating film, and the NMOS transistor is formed in each NMOS transistor region.

摘要翻译： 一种半导体器件和半导体器件的制造方法，其中半导体器件包括其中形成有PMOS晶体管区域和NMOS晶体管区域的半导体衬底，包括P型源极和漏极区域的PMOS晶体管和栅极电极，以及 形成在N型源区和漏区之间的Si沟道区上的NMOS晶体管。 PMOS晶体管形成在每个PMOS晶体管区域中，并且栅电极形成在形成在P型源区和漏区之间的SiGe沟道区上的高电介质栅极绝缘膜上。 此外，NMOS晶体管包括高电介质栅极绝缘膜和形成在栅极绝缘膜上的栅电极，并且NMOS晶体管形成在每个NMOS晶体管区域中。

公开(公告)号：US08741710B2

公开(公告)日：2014-06-03

申请号：US12248431

申请日：2008-10-09

申请人： Dong-Suk Shin ,  Ho Lee ,  Tae-Gyun Kim

发明人： Dong-Suk Shin ,  Ho Lee ,  Tae-Gyun Kim

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/8238 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/8234 ,  H01L21/823475 ,  H01L21/823871 ,  H01L29/665

摘要： Semiconductor devices are fabricated using a plasma process with a non-silane gas that includes deuterium, and which may result in improved device reliability and/or other improved device operational characteristics. One such method can include forming a gate oxide layer on a transistor region, which is defined on a substrate, and forming a gate electrode on the gate oxide layer. An etch stop layer is formed on the gate oxide layer and the gate electrode. A plasma process is performed on the interface between the gate oxide layer and the substrate using a non-silane treatment gas including deuterium. An interlayer dielectric layer is formed on the etch stop layer. A bottom metal line is formed on the interlayer dielectric layer.

摘要翻译： 使用包括氘的非硅烷气体的等离子体工艺制造半导体器件，并且其可以导致改进的器件可靠性和/或其他改进的器件操作特性。 一种这样的方法可以包括在限定在衬底上的晶体管区域上形成栅极氧化层，并在栅极氧化物层上形成栅电极。 在栅极氧化物层和栅电极上形成蚀刻停止层。 使用包括氘的非硅烷处理气体在栅极氧化物层和衬底之间的界面上进行等离子体处理。 在蚀刻停止层上形成层间电介质层。 底层金属线形成在层间电介质层上。

公开(公告)号：US07682888B2

公开(公告)日：2010-03-23

申请号：US11435968

申请日：2006-05-17

申请人： Ho Lee ,  Tetsuji Ueno ,  Hwa-Sung Rhe

发明人： Ho Lee ,  Tetsuji Ueno ,  Hwa-Sung Rhe

IPC分类号： H01L21/4763

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02293 ,  H01L21/3147 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.

摘要翻译： 形成集成电路的方法包括：在与其100°晶体取向平行的衬底上选择性地形成用于NMOS和PMOS晶体管的有源沟道区，并且选择性地形成具有碳（C）杂质的NMOS晶体管的源极/漏极区。

公开(公告)号：US07671420B2

公开(公告)日：2010-03-02

申请号：US11281599

申请日：2005-11-18

申请人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

发明人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

IPC分类号： H01L29/76 ,  H01L27/148 ,  H01L27/01

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.

摘要翻译： 公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。 表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。 根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

公开(公告)号：US07611973B2

公开(公告)日：2009-11-03

申请号：US11154236

申请日：2005-06-16

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/28044 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66628 ,  H01L29/66772

摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.

摘要翻译： 在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶 半导体图案，分别使用主半导体源气体和主蚀刻气体。 使用选择性蚀刻气体去除非单晶外延半导体层。 主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。 选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

公开(公告)号：US20090258463A1

公开(公告)日：2009-10-15

申请号：US12419698

申请日：2009-04-07

申请人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Ho Lee ,  Ji-Hye Yi

发明人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Ho Lee ,  Ji-Hye Yi

IPC分类号： H01L21/20 ,  H01L21/768

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

摘要翻译： 提供制造半导体集成电路器件的方法。 基板设置有形成在第一和第二区域上的栅极图案。 第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。 源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。 形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。 直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

公开(公告)号：US20090224287A1

公开(公告)日：2009-09-10

申请号：US12400408

申请日：2009-03-09

申请人： Dong-Suk Shin ,  Ho Lee ,  Myung-Sun Kim

发明人： Dong-Suk Shin ,  Ho Lee ,  Myung-Sun Kim

IPC分类号： H01L29/80

CPC分类号： H01L29/1083 ,  H01L21/76267 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device.

摘要翻译： 提供了具有局部掩埋绝缘层的半导体器件及其制造方法，其中在基板上形成栅电极，并将氧离子注入有源区以形成局部掩埋的绝缘层 。 在局部掩埋的绝缘层上形成杂质层以形成源极/漏极。 在源极/漏极和栅电极上形成硅化物层。 局部埋入绝缘层可以防止结漏电，降低结电容，并防止MOS晶体管的临界电压由于体偏压而增加，从而改善器件的特性。