公开(公告)号：US20130010549A1

公开(公告)日：2013-01-10

申请号：US13542487

申请日：2012-07-05

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C7/00

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/3427

摘要： A method of operating a semiconductor device according to an embodiment of the present invention includes programming selected memory cells by applying a first program voltage, which gradually rises, to a selected word line and applying a first pass voltage, which is constant, to remaining unselected word lines; and programming the selected memory cells while applying a second program voltage, which is constant, to the selected word line and applying a second pass voltage, which gradually rises, to first unselected word lines adjacent to the selected word line, when a difference between the first program voltage and the first pass voltage reaches a critical voltage difference.

摘要翻译： 根据本发明的实施例的操作半导体器件的方法包括通过对选定的字线施加逐渐上升的第一编程电压并将恒定的第一通过电压施加到剩余的未选择来对所选存储单元进行编程 字线 以及对所选择的字线施加恒定的第二编程电压，并且对所选择的字线相邻的第一未选字线施加逐渐上升的第二通过电压，对所选存储单元进行编程， 第一编程电压和第一通过电压达到临界电压差。

公开(公告)号：US20130010548A1

公开(公告)日：2013-01-10

申请号：US13542401

申请日：2012-07-05

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427

摘要： A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines.

摘要翻译： 半导体器件尤其通过以下方式操作：通过将第一编程电压施加第一步骤电压至所选择的字线并通过向未选择的字线施加具有恒定电平的第一通过电压来对选定的存储器单元进行编程;以及 当第一编程电压和第一通过电压之间的电压差达到预定的电压差时，通过将第二编程电压施加到比所述第一阶跃电压低的第二阶跃电压的第二编程电压来对所选择的存储单元进行编程， 并且通过将与第二编程电压成比例地增加的第二通过电压施加到未选择字线中与所选字线相邻的第一未选择字线。

公开(公告)号：US20120106260A1

公开(公告)日：2012-05-03

申请号：US13282029

申请日：2011-10-26

申请人： Seiichi ARITOME ,  Soo Jin Wi ,  Angelo Visconti ,  Mattia Robustelli

发明人： Seiichi ARITOME ,  Soo Jin Wi ,  Angelo Visconti ,  Mattia Robustelli

IPC分类号： G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/06 ,  G11C16/3454 ,  G11C16/3468

摘要： A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.

摘要翻译： 一种操作半导体存储器件的方法包括执行第一程序操作以提高存储单元的阈值电压，执行用于检测快速程序存储单元的程序验证操作，每个程序存储单元的阈值电压升高高于第一次验证电压 通过使用目标验证电压和顺序地低于目标验证电压的第一子验证电压和第二子验证电压，从第二子验证电压或更低的次级验证电压进行第二子验证电压，并且在 低于目标验证电压的存储单元的每个阈值电压的增量大于每个快速程序存储单元的阈值电压的增量。

公开(公告)号：US20120051139A1

公开(公告)日：2012-03-01

申请号：US13272336

申请日：2011-10-13

申请人： Seiichi ARITOME ,  Alessandro TORSI ,  Carlo MUSILLI

发明人： Seiichi ARITOME ,  Alessandro TORSI ,  Carlo MUSILLI

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.

摘要翻译： 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。

公开(公告)号：US20070128802A1

公开(公告)日：2007-06-07

申请号：US11672376

申请日：2007-02-07

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11543

摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

公开(公告)号：US20070128778A1

公开(公告)日：2007-06-07

申请号：US11672361

申请日：2007-02-07

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： H01L21/84 ,  H01L21/336 ,  H01L29/00

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11543

摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

摘要翻译： 非易失性半导体存储器包括设置在半导体衬底中的沟槽隔离和设置在半导体衬底上的层间绝缘体。 沟槽隔离限定了在半导体衬底处沿第一方向延伸的有源区。 层间绝缘体具有沿与第一方向相交的第二方向延伸的布线沟槽。 第一导电材料层设置在有源区和布线沟槽的交叉点处，使其与有源区绝缘。 第二导电材料层设置在布线沟槽中，使其与第一导电材料层绝缘。 金属层设置在布线沟槽中，使其与第二导电材料层电接触。

公开(公告)号：US20130292757A1

公开(公告)日：2013-11-07

申请号：US13605972

申请日：2012-09-06

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/66825 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/11556 ,  H01L29/66666 ,  H01L29/788 ,  H01L29/7889

摘要： A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.

摘要翻译： 半导体器件包括垂直沟道层，控制栅极和层间绝缘层，它们在衬底上彼此交替堆叠并围绕垂直沟道层，浮置栅极介于垂直沟道层与控制栅极之间，并通过层间绝缘 层和电荷阻挡层插入在浮动栅极和控制栅极之间。

公开(公告)号：US20130182504A1

公开(公告)日：2013-07-18

申请号：US13467169

申请日：2012-05-09

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C7/10 ,  G11C16/04

CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  H01L27/11519 ,  H01L27/11524

摘要： A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.

摘要翻译： 页面缓冲电路包括耦合到第一感测电路并且在其间具有第一空间的第一和第二位线以及耦合到第二感测电路以及与它们之间的第一空间的第三和第四位线。 第二位线和第三位线彼此相邻，并且第二位线和第三位线之间具有第二空间，并且第二空间小于第一空间。

公开(公告)号：US20120170378A1

公开(公告)日：2012-07-05

申请号：US13341303

申请日：2011-12-30

申请人： Seiichi ARITOME ,  Soon Ok Seo

发明人： Seiichi ARITOME ,  Soon Ok Seo

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible.

摘要翻译： 半导体存储器件的读取方法包括通过使用第一读取电压对目标单元执行读取操作，如果作为对目标单元的读取操作的结果，错误校正是可行的，则终止对目标单元的读取操作， 如果作为对目标单元的读取操作的结果，误差校正是不可行的，则对目标单元的旁边的第一单元执行读取操作，通过选择多个目标单元之一对目标单元执行再次操作 的读取电压，并且通过使用所选择的读取电压来读取目标单元的数据，并且如果纠错是可行的，则终止对目标单元的读取操作。

公开(公告)号：US20120155183A1

公开(公告)日：2012-06-21

申请号：US13325787

申请日：2011-12-14

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/14 ,  G11C16/3418

摘要： An operating method of a semiconductor memory device includes erasing all memory cells of a selected cell block, performing a soft program operation on the erased memory cells by supplying a soft program pulse to word lines of the selected cell block, performing a first verify operation using a first voltage level lower than a target voltage level of the soft program operation, performing a second verify operation using the target voltage level, setting voltages of bit lines, and repeating the soft program operation, the first verify operation, the second verify operation, and an operation of setting the voltages of bit lines while raising the soft program pulse gradually.

摘要翻译： 半导体存储器件的操作方法包括擦除所选择的单元块的所有存储单元，通过向所选择的单元块的字线提供软编程脉冲，对已擦除存储单元执行软编程操作，使用 第一电压电平低于软编程操作的目标电压电平，使用目标电压电平执行第二验证操作，设置位线的电压并重复软程序操作，第一验证操作，第二验证操作， 以及逐渐提高软程序脉冲同时设置位线的电压的操作。