公开(公告)号：US20170062421A1

公开(公告)日：2017-03-02

申请号：US15247127

申请日：2016-08-25

Applicant: IMEC VZW

Inventor： Stefan Cosemans ,  Praveen Raghavan ,  Steven Demuynck ,  Julien Ryckaert

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/743 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L28/00 ,  H01L29/785

Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.

Abstract translation: 半导体电路包括包括多个晶体管的线路前端（FEOL），每个晶体管具有源极区域，漏极区域和布置在源极区域和漏极区域之间并包括栅电极的栅极区域。 半导体电路还包括布置在FEOL中的埋入式互连件，并且从栅极区域从栅极电极的底部接触部分电连接到栅极区域。 通过使用埋地互连，可以方便地进行电路的布线。

公开(公告)号：US20230187539A1

公开(公告)日：2023-06-15

申请号：US18063859

申请日：2022-12-09

Applicant: IMEC VZW

Inventor： Sujith Subramanian ,  Hans Mertens ,  Steven Demuynck

IPC: H01L29/66 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/1033 ,  H01L29/66545

Abstract: A method for forming a first transistor structure from a first channel layer and a second transistor structure from a second channel layer is disclosed. The first channel layer and the second channel layer are vertically stacked on a substrate. The method includes processing the first transistor structure from above, followed by processing the second transistor structure from the backside.

公开(公告)号：US20230187528A1

公开(公告)日：2023-06-15

申请号：US18065122

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Sujith Subramanian ,  Steven Demuynck ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66545

Abstract: The disclosed method includes forming an initial layer stack comprising a sacrificial layer of a first semiconductor material and over the sacrificial layer a channel layer of a second semiconductor material, forming a fin structures by patterning trenches in the initial layer stack, forming an anchoring structure extending across the fin structures, and while the channel layers are anchored by the anchoring structure: removing the sacrificial layers by a selective etching of the first semiconductor material, thereby forming a longitudinal cavity underneath the channel layer of each fin structure, and depositing an insulating material to fill the cavities, wherein the insulating material is formed of a flowable dielectric, and subsequently recessing the at least one anchoring structure and the insulating material to a level below the cavities such that the insulating material remains in the cavities to form insulating layers underneath the channel layers of each fin structure.

公开(公告)号：US11348842B2

公开(公告)日：2022-05-31

申请号：US17074047

申请日：2020-10-19

Applicant: IMEC VZW

Inventor： Eugenio Dentoni Litta ,  Boon Teik Chan ,  Steven Demuynck

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.

公开(公告)号：US11107812B2

公开(公告)日：2021-08-31

申请号：US16696935

申请日：2019-11-26

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Steven Demuynck

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

公开(公告)号：US10128124B2

公开(公告)日：2018-11-13

申请号：US14964406

申请日：2015-12-09

Applicant: IMEC VZW

Inventor： Eddy Kunnen ,  Steven Demuynck ,  Jürgen Bömmels

IPC: H01L21/311 ,  H01L21/768

Abstract: A method is provided for blocking a portion of a longitudinal through-hole during manufacture of a semiconductor structure, comprising the steps of: forming a stack comprising a hard mask comprising at least one trench, and a first coating filling the at least one trench and coating the hard mask, wherein the first coating comprises one or more materials that can be etched selectively with respect to a second coating; etching at least one vertical via in the first coating directly above the portion of the trench in such a way as to remove the first coating over at least a fraction of the depth of the trench, filling the at least one via with the second coating material, and removing the first coating selectively with respect to the second coating from at least the one or more longitudinal through-holes in such a way as to leave in place any of the first coating present directly underneath the second coating.

公开(公告)号：US10043798B2

公开(公告)日：2018-08-07

申请号：US15247127

申请日：2016-08-25

Applicant: IMEC VZW

Inventor： Stefan Cosemans ,  Praveen Raghavan ,  Steven Demuynck ,  Julien Ryckaert

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L21/74 ,  H01L29/78

Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.