公开(公告)号：US10332588B2

公开(公告)日：2019-06-25

申请号：US15851531

申请日：2017-12-21

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

IPC: G11C11/412 ,  H01L27/11 ,  H01L29/423 ,  G11C11/408 ,  H01L29/08 ,  H01L27/06 ,  H01L29/06

Abstract: In an aspect of the disclosed technology, a SRAM device includes a first stack of transistors and a second stack of transistors arranged on a substrate. Each of the first and second stacks includes a pull-up transistor, a pull-down transistor and a pass transistor, where each of the transistors includes a horizontally extending channel. In each of the first and second stacks, the pull-up transistor and the pull-down transistor have a common gate electrode extending vertically therebetween, and the pass transistor has a gate electrode separated from the common gate electrode. A source/drain of each of the pull-up transistor and the pull-down transistor and a source/drain of the pass transistor included in one of the first stack and the second stack are electrically interconnected with the common gate electrode of the pull-up transistor and the pull-down transistor included in the other of the first stack and the second stack.

公开(公告)号：US20160283629A1

公开(公告)日：2016-09-29

申请号：US15081635

申请日：2016-03-25

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Pieter Weckx ,  Dmitrios Rodopoulos ,  Benjamin Kaczer ,  Francky Catthoor

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/76 ,  G06F2217/80 ,  G06F2217/82

Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

Abstract translation: 公开了一种用于模拟电子电路的系统和方法。 该方法包括创建从n维参数空间内选择的电路或设备参数点的有限集合。 该方法包括针对该组的每个电路或设备参数点确定性能度量的对应响应值和相应的发生概率。 该方法包括针对性能度量的预定值确定总出现概率。

公开(公告)号：US12164849B2

公开(公告)日：2024-12-10

申请号：US17039571

申请日：2020-09-30

Applicant: IMEC vzw

Inventor： Subrat Mishra ,  Pieter Weckx ,  Francky Catthoor ,  Alessio Spessot

IPC: G06F30/3308 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06F115/06 ,  G06F119/04

Abstract: A system and method of simulating device aging based on a digital waveform representative of a workload of an electronic device are disclosed. In one aspect, the method comprises grouping contiguous sets of cycles into segments, each set corresponding to a segment. Each segment has values for a combination of segment parameters that are unique from each of the other segments and a start point that is separated from a start point of an adjacent segment by a pre-defined distance criterion. Grouping the sets into the segments comprises, for each segment: sampling one or more sequential cycles of the workload, generating the segment based on the sampled contiguous cycles having a period exceeding a threshold period, and determining the values for the combination of segment parameters. The method further comprises applying an aging model to the segments to simulate the aging. The segments are a representation of the digital waveform.

公开(公告)号：US20230178554A1

公开(公告)日：2023-06-08

申请号：US18060785

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Bilal Chehab ,  Pieter Schuddinck ,  Julien Ryckaert ,  Pieter Weckx

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392

Abstract: Example embodiments relate to complementary field-effect transistor (CFET) devices. An example CFET device includes a bottom FET device. The bottom FET device includes a bottom channel nanostructure having a first side surface oriented in a first direction. The bottom FET device also includes a second side surface oriented in a second direction opposite the first direction. Further, the bottom FET device includes a bottom gate electrode configured to define a tri-gate or a gate-all-around with respect to the bottom channel nanostructure. The bottom gate electrode includes a side gate portion arranged along the first side surface of the bottom channel nanostructure. The CFET device also includes a top FET device stacked on the bottom FET device. The top FET device includes channel layers, a gate electrode, and gate prongs. Additionally, the CFET device includes a top gate contact via. Further, the CFET device includes a bottom gate contact via.

公开(公告)号：US11515399B2

公开(公告)日：2022-11-29

申请号：US17112844

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L21/02 ,  H01L21/8238

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

公开(公告)号：US11164942B1

公开(公告)日：2021-11-02

申请号：US16885040

申请日：2020-05-27

Applicant: IMEC VZW

Inventor： Pieter Weckx ,  Julien Ryckaert ,  Eugenio Dentoni Litta

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/311 ,  H01L29/66

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second nanosheet transistor structure, each comprising a source, a drain, and a channel extending between the source and the drain in a first direction, and a gate extending across the channel, wherein the first and second nanosheet transistor structures are spaced apart in a second direction, transverse to the first direction, by an insulating wall extending in the first direction.

公开(公告)号：US20210193821A1

公开(公告)日：2021-06-24

申请号：US17112844

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L21/02 ,  H01L21/8238

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

公开(公告)号：US20190386011A1

公开(公告)日：2019-12-19

申请号：US16441725

申请日：2019-06-14

Applicant: IMEC vzw

Inventor： Pieter Weckx ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L27/11 ,  G11C5/02 ,  G11C5/06 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8238

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.