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    Static random access memory device having interconnected stacks of transistors
    1.
    发明授权
    Static random access memory device having interconnected stacks of transistors 有权

    公开(公告)号：US10332588B2

    公开(公告)日：2019-06-25

    申请号：US15851531

    申请日：2017-12-21

    Applicant: IMEC VZW ,  Vrije Universiteit Brussel

    Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

    IPC: G11C11/412 ,  H01L27/11 ,  H01L29/423 ,  G11C11/408 ,  H01L29/08 ,  H01L27/06 ,  H01L29/06

    Abstract: In an aspect of the disclosed technology, a SRAM device includes a first stack of transistors and a second stack of transistors arranged on a substrate. Each of the first and second stacks includes a pull-up transistor, a pull-down transistor and a pass transistor, where each of the transistors includes a horizontally extending channel. In each of the first and second stacks, the pull-up transistor and the pull-down transistor have a common gate electrode extending vertically therebetween, and the pass transistor has a gate electrode separated from the common gate electrode. A source/drain of each of the pull-up transistor and the pull-down transistor and a source/drain of the pass transistor included in one of the first stack and the second stack are electrically interconnected with the common gate electrode of the pull-up transistor and the pull-down transistor included in the other of the first stack and the second stack.

    STATIC RANDOM ACCESS MEMORY CELL
    2.
    发明申请
    STATIC RANDOM ACCESS MEMORY CELL 审中-公开

    公开(公告)号：US20180174642A1

    公开(公告)日：2018-06-21

    申请号：US15851531

    申请日：2017-12-21

    Applicant: IMEC VZW ,  Vrije Universiteit Brussel

    Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

    IPC: G11C11/412 ,  H01L27/11 ,  G11C11/408 ,  H01L29/08 ,  H01L29/423

    CPC classification number: G11C11/412 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

    Abstract: The disclosed technology generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) device. One aspect of the disclosed technology is a bit cell for a static random access memory (SRAM) comprising: a first and a second vertical stack of transistors arranged on a substrate. Each stack includes a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a horizontally extending channel, the pull-up transistor and the pull-down transistor having a common gate electrode extending vertically between the pull-up transistor and the pull-down transistor and the pass transistor having a gate electrode being separate from the common gate electrode. A source/drain of the pull-up transistor and of the pull-down transistor of the first stack, a source/drain of the pass transistor of the first stack and the common gate electrode of the pull-up and pull-down transistors of the second stack are electrically interconnected. A source/drain of the pull-up transistor and of the pull-down transistor of the second stack, a source/drain of the pass transistor of the second stack and the common gate electrode of the pull-up and pull-down transistors of the first stack are electrically interconnected.

    INTEGRATED CIRCUIT POWER DISTRIBUTION NETWORK
    4.
    发明申请
    INTEGRATED CIRCUIT POWER DISTRIBUTION NETWORK 审中-公开

    公开(公告)号：US20170294448A1

    公开(公告)日：2017-10-12

    申请号：US15479633

    申请日：2017-04-05

    Applicant: IMEC VZW

    Inventor： Peter Debacker ,  Praveen Raghavan ,  Vassilios Constantinos Gerousis

    IPC: H01L27/118

    Abstract: An integrated circuit (IC) power distribution network is disclosed. In one aspect, the IC includes a stack of layers formed on a substrate. The IC includes standard cells with parallel gate structures oriented in a direction y. Each cell includes an internal power pin for supplying a reference voltage to the cell. The stack includes metal layers in which lines are formed to route signals between cells. The lines in each metal layer have a preferred orientation that is orthogonal to that of the lines in an adjacent metal layer. A first layer is the lowest metal layer that has y as a preferred orientation while also providing routing resources for signal routing between the cells. A second layer is the nearest metal layer above this first layer. The IC includes a power distribution network for delivering the reference voltage to the power pin.

    Double-gate vertical transistor semiconductor device
    6.
    发明授权
    Double-gate vertical transistor semiconductor device 有权

    公开(公告)号：US10355128B2

    公开(公告)日：2019-07-16

    申请号：US15835703

    申请日：2017-12-08

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Praveen Raghavan ,  Odysseas Zografos

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

    Abstract: A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.

    Convolution engine for neural networks
    9.
    发明授权
    Convolution engine for neural networks 有权

    公开(公告)号：US11475101B2

    公开(公告)日：2022-10-18

    申请号：US16685892

    申请日：2019-11-15

    Applicant: IMEC VZW

    Inventor： Francky Catthoor ,  Praveen Raghavan ,  Dimitrios Rodopoulos ,  Mohit Dandekar

    IPC: G06F17/15 ,  G06N3/04 ,  G06N3/08

    Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.

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