公开(公告)号：US09378785B2

公开(公告)日：2016-06-28

申请号：US13974001

申请日：2013-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chih-He Lin ,  Sih-Han Li ,  Wen-Pin Lin ,  Shyh-Shyuan Sheu

IPC: G11C11/00 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C7/1072 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

Abstract: A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.

Abstract translation: 电阻式随机存取存储器件包括存储器阵列，读取电路，回写逻辑电路和回写电路。 读取电路读取存储在所选择的存储器单元中的数据，并且相应地产生第一控制信号。 回写逻辑电路根据第一控制信号和第二控制信号产生回写控制信号。 回写电路根据回写控制信号和回写电压对所选择的存储单元执行写回操作，以将所选存储单元的电阻状态从低电阻状态改变为 并且根据所选存储单元的电阻状态产生第二控制信号。

公开(公告)号：US20180136010A1

公开(公告)日：2018-05-17

申请号：US15607389

申请日：2017-05-26

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shyh-Shyuan Sheu ,  Ya-Wen Yang ,  Chih-Ping Cheng ,  Chih-Sheng Lin

IPC: G01D3/02 ,  H03K17/30 ,  G01D18/00

CPC classification number: G01D3/022 ,  G01B2210/60 ,  G01D18/008 ,  H03K17/30

Abstract: A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.

公开(公告)号：US08942027B1

公开(公告)日：2015-01-27

申请号：US13939062

申请日：2013-07-10

Applicant: Industrial Technology Research Institute

Inventor： Ching-Hao Chuang ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Zhe-Hui Lin

IPC: G11C11/00 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081

Abstract: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Abstract translation: 存储器存储电路包括易失性存储器部分，控制部分和非易失性存储器部分。 易失性存储器部分包括存储一对互补逻辑数据的第一节点和第二节点。 控制部分包括第一晶体管和第二晶体管。 第一晶体管和第二晶体管的栅电极被耦合以接收存储信号，并且第一和第二晶体管的第一电极被耦合以接收控制信号。 非易失性存储器部分包括第一电阻存储器元件和第二电阻存储元件，用于存储该对互补逻辑数据。 第一电阻性存储元件耦合在第一晶体管的第二电极和第一节点之间，而第二电阻存储元件耦合在第二晶体管的第二电极和第二节点之间。

公开(公告)号：US20150016176A1

公开(公告)日：2015-01-15

申请号：US13939062

申请日：2013-07-10

Applicant: Industrial Technology Research Institute

Inventor： Ching-Hao Chuang ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Zhe-Hui Lin

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081

Abstract: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Abstract translation: 存储器存储电路包括易失性存储器部分，控制部分和非易失性存储器部分。 易失性存储器部分包括存储一对互补逻辑数据的第一节点和第二节点。 控制部分包括第一晶体管和第二晶体管。 第一晶体管和第二晶体管的栅电极被耦合以接收存储信号，并且第一和第二晶体管的第一电极被耦合以接收控制信号。 非易失性存储器部分包括第一电阻存储器元件和第二电阻存储元件，用于存储该对互补逻辑数据。 第一电阻性存储元件耦合在第一晶体管的第二电极和第一节点之间，而第二电阻存储元件耦合在第二晶体管的第二电极和第二节点之间。

公开(公告)号：US12260321B2

公开(公告)日：2025-03-25

申请号：US17385316

申请日：2021-07-26

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Fu-Cheng Tsai ,  Yi-Ching Kuo ,  Chih-Sheng Lin ,  Shyh-Shyuan Sheu ,  Tay-Jyi Lin ,  Shih-Chieh Chang

IPC: H03M1/12 ,  G06N3/04 ,  G06N3/063 ,  G11C27/02

Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

公开(公告)号：US10914618B2

公开(公告)日：2021-02-09

申请号：US15851609

申请日：2017-12-21

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Ya-Wen Yang ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

IPC: G01D18/00 ,  G01D3/02

Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

公开(公告)号：US20210004678A1

公开(公告)日：2021-01-07

申请号：US16846427

申请日：2020-04-13

Applicant: Industrial Technology Research Institute

Inventor： Shih-Chieh Chang ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Heng-Yuan Lee

IPC: G06N3/08 ,  G11C11/54 ,  G06N3/04

Abstract: A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.

公开(公告)号：US08872543B2

公开(公告)日：2014-10-28

申请号：US13872168

申请日：2013-04-29

Applicant: Industrial Technology Research Institute

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Shyh-Shyuan Sheu ,  Hsin-Chi Lai

IPC: H03K19/173 ,  G06F7/38 ,  H03K19/177

CPC classification number: H03K19/1776

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract translation: 提供了可配置逻辑块（CLB）和CLB的操作方法。 CLB包括存储单元和选择电路。 存储单元包括第一电阻性非易失性存储器（RNVM）元件和第二RNVM元件。 第一和第二RNVM元件的顶部电极（TE）耦合到存储器单元的输出端子。 第一和第二RNVM元件的底部电极（BE）分别耦合到存储器单元的第一偏置端子和第二偏置端子。 选择电路根据输入逻辑值选择一个存储器单元，并根据所选存储器单元的输出逻辑值确定CLB的输出逻辑值。

公开(公告)号：US20140210514A1

公开(公告)日：2014-07-31

申请号：US13872168

申请日：2013-04-29

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Shyh-Shyuan Sheu ,  Hsin-Chi Lai

IPC: H03K19/177

CPC classification number: H03K19/1776

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract translation: 提供了可配置逻辑块（CLB）和CLB的操作方法。 CLB包括存储单元和选择电路。 存储单元包括第一电阻性非易失性存储器（RNVM）元件和第二RNVM元件。 第一和第二RNVM元件的顶部电极（TE）耦合到存储器单元的输出端子。 第一和第二RNVM元件的底部电极（BE）分别耦合到存储器单元的第一偏置端子和第二偏置端子。 选择电路根据输入逻辑值选择一个存储器单元，并根据所选存储器单元的输出逻辑值确定CLB的输出逻辑值。

公开(公告)号：US10324054B2

公开(公告)日：2019-06-18

申请号：US16178599

申请日：2018-11-02

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

Abstract: A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.