公开(公告)号：US20140284771A1

公开(公告)日：2014-09-25

申请号：US14296006

申请日：2014-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gunther Mackh ,  Adolf Koller

IPC: H01L23/29 ,  H01L23/00

CPC classification number: H01L23/29 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.

Abstract translation: 一种用于制造多个芯片的方法包括提供包括由一个或多个切割线分开的多个芯片区域的晶片的步骤，其中芯片区域布置在第一主表面上，提供激光吸收层的步骤 与第一主表面相对的第二主表面和在激光吸收层上提供背侧金属叠层的步骤。 之后，通过使用隐形切割，沿着切割线将芯片沿着切割线施加到激光吸收层。

公开(公告)号：US20140170836A1

公开(公告)日：2014-06-19

申请号：US14184856

申请日：2014-02-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gunther Mackh ,  Gerhard Leschik ,  Adolf Koller ,  Harald Seidl

IPC: H01L21/78

CPC classification number: H01L21/78 ,  G06F17/5068 ,  H01L21/82 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.

Abstract translation: 芯片包括电介质层中的电介质层和填充结构，其中填充结构沿着芯片的切割边缘延伸，填充结构邻接切割边缘。

公开(公告)号：US10043701B2

公开(公告)日：2018-08-07

申请号：US13895241

申请日：2013-05-15

Applicant: Infineon Technologies AG

Inventor： Adolf Koller ,  Franco Mariani ,  Katharina Umminger

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/67

Abstract: Methods and apparatuses are provided where a parting agent is applied to at least one portion of a substrate. The at least one portion of the substrate is removed from a carrier.

公开(公告)号：US20180204808A1

公开(公告)日：2018-07-19

申请号：US15872322

申请日：2018-01-16

Applicant: Infineon Technologies AG

Inventor： Franco Mariani ,  Adolf Koller

IPC: H01L23/00 ,  H01L21/268 ,  H01L29/04 ,  H01L21/78 ,  H01L23/58

Abstract: A circumferential embedded structure is formed by laser irradiation in a semiconductor substrate, which is of a semiconductor material. The embedded structure includes a polycrystalline structure of the semiconductor material, and surrounds a central portion of a semiconductor die. The semiconductor die including the embedded structure is separated from the semiconductor substrate.

公开(公告)号：US20170349432A1

公开(公告)日：2017-12-07

申请号：US15613666

申请日：2017-06-05

Applicant: Infineon Technologies AG

Inventor： Adolf Koller ,  Bernhard Drummer

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00825 ,  B81B7/0016

Abstract: A method of removing a reinforcement ring from a wafer is described. The method includes forming a ring-shaped recess in a first surface of the wafer and separating the reinforcement ring from an inner region of the wafer along the ring-shaped recess.

公开(公告)号：US20140117505A1

公开(公告)日：2014-05-01

申请号：US13665501

申请日：2012-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gunther Mackh ,  Adolf Koller

IPC: H01L21/78 ,  H01L23/00

CPC classification number: H01L23/29 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.

Abstract translation: 一种用于制造多个芯片的方法包括提供包括由一个或多个切割线分开的多个芯片区域的晶片的步骤，其中芯片区域布置在第一主表面上，提供激光吸收层的步骤 与第一主表面相对的第二主表面和在激光吸收层上提供背侧金属叠层的步骤。 之后，通过使用隐形切割，沿着切割线将芯片沿着切割线施加到激光吸收层。

公开(公告)号：US20140099777A1

公开(公告)日：2014-04-10

申请号：US13648216

申请日：2012-10-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gunther Mackh ,  Maria Heidenblut ,  Adolf Koller ,  Anatoly Sotnikov

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.

Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底的第一侧上和/或之上形成凹槽。 使用激光工艺从基板的第二侧形成切割层。 第二面与第一面相对。 切割层设置在基板内的凹槽下方。 通过切割层将衬底分离。

公开(公告)号：US10748801B2

公开(公告)日：2020-08-18

申请号：US15939921

申请日：2018-03-29

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Markus Brunnbauer ,  Adolf Koller ,  Jochen Mueller

IPC: H01L21/683 ,  H01L29/36 ,  H01L21/268 ,  H01L21/78

Abstract: According to various embodiments, a method for processing a carrier may include: forming an arrangement of defects in the carrier, wherein a surface region of the carrier is disposed over the arrangement of defects at a first surface of the carrier, wherein the arrangement of defects is configured to generate a crack structure extending from the arrangement of defects into the surface region; partially removing the carrier to remove the arrangement of defects; and separating the surface region of the carrier into a plurality of surface region portions along the crack structure.

公开(公告)号：US20180286735A1

公开(公告)日：2018-10-04

申请号：US15939921

申请日：2018-03-29

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Markus Brunnbauer ,  Adolf Koller ,  Jochen Mueller

IPC: H01L21/683 ,  H01L21/78 ,  H01L29/36 ,  H01L21/268

Abstract: According to various embodiments, a method for processing a carrier may include: forming an arrangement of defects in the carrier, wherein a surface region of the carrier is disposed over the arrangement of defects at a first surface of the carrier, wherein the arrangement of defects is configured to generate a crack structure extending from the arrangement of defects into the surface region; partially removing the carrier to remove the arrangement of defects; and separating the surface region of the carrier into a plurality of surface region portions along the crack structure.

公开(公告)号：US20180233470A1

公开(公告)日：2018-08-16

申请号：US15897654

申请日：2018-02-15

Applicant: Infineon Technologies AG

Inventor： Thomas Killer ,  Markus Brunnbauer ,  Marina Janker ,  Adolf Koller ,  Gabriel Maier ,  Andreas Mueller-Hipper ,  Andreas Stueckjuergen ,  Christine Thoms

IPC: H01L23/00 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L24/11 ,  H01L21/3065 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/023 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16221 ,  H01L2224/16238 ,  H01L2224/81097 ,  H01L2224/94 ,  H01L2924/1304 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method is provided which comprises forming recesses in a front side of a wafer, connecting a first temporary holding body to the front side of the recessed wafer, thereafter thinning the wafer from a back side, connecting a second temporary holding body to the back side, and thereafter removing the first temporary holding body.