公开(公告)号：US10043701B2

公开(公告)日：2018-08-07

申请号：US13895241

申请日：2013-05-15

Applicant: Infineon Technologies AG

Inventor： Adolf Koller ,  Franco Mariani ,  Katharina Umminger

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/67

Abstract: Methods and apparatuses are provided where a parting agent is applied to at least one portion of a substrate. The at least one portion of the substrate is removed from a carrier.

公开(公告)号：US11916059B2

公开(公告)日：2024-02-27

申请号：US17411060

申请日：2021-08-25

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Stefan Pompl ,  Damian Sojka ,  Katharina Umminger

IPC: H01L23/60 ,  H01L27/02 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L29/74 ,  H02H9/04 ,  H01L27/07

CPC classification number: H01L27/0248 ,  H01L21/78 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/60 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/7416 ,  H02H9/04 ,  H01L27/0744 ,  H01L29/74 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/30205 ,  H01L2924/1301 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.

公开(公告)号：US10128204B2

公开(公告)日：2018-11-13

申请号：US15730466

申请日：2017-10-11

Applicant: Infineon Technologies AG

Inventor： Carsten Ahrens ,  Katharina Umminger ,  Carsten von Koblinski

IPC: H01L21/70 ,  H01L23/66 ,  H01L23/522 ,  H01L23/64 ,  H01L25/11

Abstract: In accordance with an embodiment, an RF module includes a bulk semiconductor substrate with at least one integrated RF component integrated in a first main surface region of the bulk semiconductor substrate; an insulator structure surrounding a side surface region of the bulk semiconductor substrate; a wiring layer stack including at least one structured metallization layer embedded into an insulation material, the wiring layer stack being arranged on the first main surface region of the bulk semiconductor substrate and a first main surface region of the insulator structure; and a carrier structure at a second main surface region of the insulator structure, wherein the carrier structure and the insulator structure include different materials.

公开(公告)号：US11127733B2

公开(公告)日：2021-09-21

申请号：US16783188

申请日：2020-02-06

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Stefan Pompl ,  Damian Sojka ,  Katharina Umminger

IPC: H01L27/02 ,  H01L23/60 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L29/74 ,  H02H9/04 ,  H01L27/07

Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.

公开(公告)号：US20180108622A1

公开(公告)日：2018-04-19

申请号：US15730466

申请日：2017-10-11

Applicant: Infineon Technologies AG

Inventor： Carsten Ahrens ,  Katharina Umminger ,  Carsten von Koblinski

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/64 ,  H01L25/11

CPC classification number: H01L23/66 ,  H01L21/6835 ,  H01L23/5222 ,  H01L23/645 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1423 ,  H01L2924/1431 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/03 ,  H01L2224/11

Abstract: In accordance with an embodiment, an RF module includes a bulk semiconductor substrate with at least one integrated RF component integrated in a first main surface region of the bulk semiconductor substrate; an insulator structure surrounding a side surface region of the bulk semiconductor substrate; a wiring layer stack including at least one structured metallization layer embedded into an insulation material, the wiring layer stack being arranged on the first main surface region of the bulk semiconductor substrate and a first main surface region of the insulator structure; and a carrier structure at a second main surface region of the insulator structure, wherein the carrier structure and the insulator structure include different materials.

公开(公告)号：US09576875B2

公开(公告)日：2017-02-21

申请号：US14591014

申请日：2015-01-07

Applicant: Infineon Technologies AG

Inventor： Reinhard Hess ,  Katharina Umminger ,  Gabriel Maier ,  Markus Menath ,  Gunther Mackh ,  Hannes Eder ,  Alexander Heinrich

IPC: H01L23/31 ,  H01L23/485 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/3171 ,  H01L21/02107 ,  H01L21/30655 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/485 ,  H01L24/05 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05548 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract translation: 提供了一种制造芯片布置的方法，该方法包括：在载体中形成一个孔，该载体包括至少一个芯片，其中在载体中形成孔包括：选择性地去除载体材料，从而在载体中形成空腔，形成钝化 通过选择性去除载体材料暴露的一个或多个腔壁上的材料; 选择性地去除钝化材料的一部分和通过选择性去除钝化材料暴露的另外的载体材料，其中钝化材料的另一部分保留在至少一个空腔侧壁上; 该方法还包括随后在保留在至少一个空腔侧壁上的钝化材料的另一部分上形成层。

公开(公告)号：US20140338827A1

公开(公告)日：2014-11-20

申请号：US13895241

申请日：2013-05-15

Applicant: Infineon Technologies AG

Inventor： Adolf Koller ,  Franco Mariani ,  Katharina Umminger

IPC: H01L21/683

CPC classification number: H01L21/6836 ,  H01L21/67115 ,  H01L21/67132 ,  H01L2221/68327 ,  H01L2221/68381 ,  Y10T156/1917 ,  Y10T156/1994

Abstract: Methods and apparatuses are provided where a parting agent is applied to at least one portion of a substrate. The at least one portion of the substrate is removed from a carrier.

Abstract translation: 提供了将分离剂施加到基底的至少一部分的方法和装置。 将衬底的至少一部分从载体上去除。