公开(公告)号：US09972535B2

公开(公告)日：2018-05-15

申请号：US15596938

申请日：2017-05-16

Applicant: Infineon Technologies AG

Inventor： Markus Brunnbauer ,  Franco Mariani

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5442

Abstract: Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions parallel to the main surface. At least some of the separation grooves are spaced from a lateral outer surface of the semiconductor substrate by at most a first distance. An indentation is formed along a lateral surface. The indentation extends from the main surface into the semiconductor substrate. A minimum horizontal indentation width of the indentation is equal to or greater than the first distance. A with respect to the main surface vertical extension of the indentation is equal to or greater than a vertical extension of the separation grooves.

公开(公告)号：US10748801B2

公开(公告)日：2020-08-18

申请号：US15939921

申请日：2018-03-29

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Markus Brunnbauer ,  Adolf Koller ,  Jochen Mueller

IPC: H01L21/683 ,  H01L29/36 ,  H01L21/268 ,  H01L21/78

Abstract: According to various embodiments, a method for processing a carrier may include: forming an arrangement of defects in the carrier, wherein a surface region of the carrier is disposed over the arrangement of defects at a first surface of the carrier, wherein the arrangement of defects is configured to generate a crack structure extending from the arrangement of defects into the surface region; partially removing the carrier to remove the arrangement of defects; and separating the surface region of the carrier into a plurality of surface region portions along the crack structure.

公开(公告)号：US20180286735A1

公开(公告)日：2018-10-04

申请号：US15939921

申请日：2018-03-29

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Markus Brunnbauer ,  Adolf Koller ,  Jochen Mueller

IPC: H01L21/683 ,  H01L21/78 ,  H01L29/36 ,  H01L21/268

Abstract: According to various embodiments, a method for processing a carrier may include: forming an arrangement of defects in the carrier, wherein a surface region of the carrier is disposed over the arrangement of defects at a first surface of the carrier, wherein the arrangement of defects is configured to generate a crack structure extending from the arrangement of defects into the surface region; partially removing the carrier to remove the arrangement of defects; and separating the surface region of the carrier into a plurality of surface region portions along the crack structure.

公开(公告)号：US20180233470A1

公开(公告)日：2018-08-16

申请号：US15897654

申请日：2018-02-15

Applicant: Infineon Technologies AG

Inventor： Thomas Killer ,  Markus Brunnbauer ,  Marina Janker ,  Adolf Koller ,  Gabriel Maier ,  Andreas Mueller-Hipper ,  Andreas Stueckjuergen ,  Christine Thoms

IPC: H01L23/00 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L24/11 ,  H01L21/3065 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/023 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16221 ,  H01L2224/16238 ,  H01L2224/81097 ,  H01L2224/94 ,  H01L2924/1304 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method is provided which comprises forming recesses in a front side of a wafer, connecting a first temporary holding body to the front side of the recessed wafer, thereafter thinning the wafer from a back side, connecting a second temporary holding body to the back side, and thereafter removing the first temporary holding body.

公开(公告)号：US09570352B2

公开(公告)日：2017-02-14

申请号：US14964603

申请日：2015-12-10

Applicant: Infineon Technologies AG

Inventor： Markus Brunnbauer ,  Bernhard Drummer ,  Korbinian Kaspar ,  Gunther Mackh

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/6836 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

Abstract translation: 切割晶片的方法可以包括在晶片中形成多个有源区，每个有源区包括至少一个电子部件，所述有源区从晶片的第一表面延伸到晶片高度并通过分离分离 区域，所述分离区域不含金属，通过在与所述晶片的第一表面的至少一个分离区域中的等离子体蚀刻在所述晶片中形成至少一个沟槽。 所述至少一个沟槽比所述多个有源区域延伸进入所述晶片。 该方法还可以包括在分离区域中处理晶片的剩余部分以将晶片分离成单独的芯片。

公开(公告)号：US10373871B2

公开(公告)日：2019-08-06

申请号：US15968312

申请日：2018-05-01

Applicant: Infineon Technologies AG

Inventor： Markus Brunnbauer ,  Franco Mariani

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/683 ,  H01L23/544

Abstract: Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions parallel to the main surface. At least some of the separation grooves are spaced from a lateral outer surface of the semiconductor substrate by at most a first distance. An indentation is formed along a lateral surface. The indentation extends from the main surface into the semiconductor substrate. A minimum horizontal indentation width of the indentation is equal to or greater than the first distance. A with respect to the main surface vertical extension of the indentation is equal to or greater than a vertical extension of the separation grooves.

公开(公告)号：US20170345716A1

公开(公告)日：2017-11-30

申请号：US15596938

申请日：2017-05-16

Applicant: Infineon Technologies AG

Inventor： Markus Brunnbauer ,  Franco Mariani

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/308 ,  H01L23/544 ,  H01L21/683 ,  H01L21/306

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5442

Abstract: Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions parallel to the main surface. At least some of the separation grooves are spaced from a lateral outer surface of the semiconductor substrate by at most a first distance. An indentation is formed along a lateral surface. The indentation extends from the main surface into the semiconductor substrate. A minimum horizontal indentation width of the indentation is equal to or greater than the first distance. A with respect to the main surface vertical extension of the indentation is equal to or greater than a vertical extension of the separation grooves.

公开(公告)号：US20170309577A1

公开(公告)日：2017-10-26

申请号：US15137396

申请日：2016-04-25

Applicant: Infineon Technologies AG

Inventor： Markus Brunnbauer

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/308 ,  H01L23/58 ,  H01L21/306

CPC classification number: H01L23/562 ,  H01L21/02002 ,  H01L21/30625 ,  H01L21/308 ,  H01L21/32051 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/585 ,  H01L2924/1461 ,  H01L2924/3511

Abstract: A method for use in manufacturing semiconductor devices includes providing a wafer includes a semiconductor substrate that is mechanically homogeneous. The method further comprises forming a mechanical structure in the semiconductor substrate. In a wafer comprising a semiconductor device on a semiconductor substrate, the semiconductor substrate includes a mechanical structure. In a die comprising a semiconductor device on a semiconductor substrate, the semiconductor substrate includes a mechanical structure.

公开(公告)号：US20180247872A1

公开(公告)日：2018-08-30

申请号：US15968312

申请日：2018-05-01

Applicant: Infineon Technologies AG

Inventor： Markus Brunnbauer ,  Franco Mariani

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/308 ,  H01L21/683 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5442

Abstract: Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions parallel to the main surface. At least some of the separation grooves are spaced from a lateral outer surface of the semiconductor substrate by at most a first distance. An indentation is formed along a lateral surface. The indentation extends from the main surface into the semiconductor substrate. A minimum horizontal indentation width of the indentation is equal to or greater than the first distance. A with respect to the main surface vertical extension of the indentation is equal to or greater than a vertical extension of the separation grooves.

公开(公告)号：US09911655B2

公开(公告)日：2018-03-06

申请号：US15390767

申请日：2016-12-27

Applicant: Infineon Technologies AG

Inventor： Markus Brunnbauer ,  Bernhard Drummer ,  Korbinian Kaspar ,  Gunther Mackh

IPC: H01L29/06 ,  H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/6836 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.