公开(公告)号：US20170336854A1

公开(公告)日：2017-11-23

申请号：US15529792

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Arojit Roychowdhury ,  Ramanathan Sethuraman ,  Ajaya V. Durg ,  Rakesh A. Ughreja

IPC: G06F1/32 ,  G06F15/78 ,  G11C5/14

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3296 ,  G06F15/781 ,  G11C5/148 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170228014A1

公开(公告)日：2017-08-10

申请号：US15494625

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0808

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/314 ,  G06F2212/621 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US20170103036A1

公开(公告)日：2017-04-13

申请号：US15122575

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Sundar Iyer ,  Rajasekaran Andiappan ,  Ajaya V. Durg ,  Kenneth P. Foust ,  Bruce L. Fleming

IPC: G06F13/42 ,  G06F13/40 ,  G06F1/32 ,  G06F13/364 ,  G06F13/26

CPC classification number: G06F13/4282 ,  G06F1/3287 ,  G06F13/26 ,  G06F13/364 ,  G06F13/404 ,  G06F13/4295 ,  G06F2213/0016

Abstract: In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.