公开(公告)号：US20210074338A1

公开(公告)日：2021-03-11

申请号：US16562745

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Ravi H. MOTWANI ,  Chang Wan HA

IPC: G11C7/12 ,  G11C29/44 ,  G11C16/34 ,  G11C16/14 ,  G06F11/07

Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

公开(公告)号：US20190296184A1

公开(公告)日：2019-09-26

申请号：US16439341

申请日：2019-06-12

Applicant: Intel Corporation

Inventor： Khaled AHMED ,  Anup PANCHOLI ,  Ali KHAKIFIROOZ

IPC: H01L33/00 ,  H01L23/00

Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, method of manufacturing a micro-light emitting diode (LED) display panel includes positioning a display backplane substrate in a tank or container, the display backplane substrate having microgrooves therein. The method also includes adding a fluid to the tank or container, the fluid including a suspension of light-emitting diode (LED) pixel elements therein. The method also includes moving the fluid over the display backplane substrate. The method also includes assembling LED pixel elements from the fluid into corresponding ones of the microgrooves.

公开(公告)号：US20190103159A1

公开(公告)日：2019-04-04

申请号：US15720492

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Ali KHAKIFIROOZ ,  Rohit S. SHENOY ,  Pranav KALAVADE ,  Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/04

Abstract: Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.

公开(公告)号：US20190006016A1

公开(公告)日：2019-01-03

申请号：US15638260

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Shantanu R. RAJWADE ,  Aliasgar S. MADRASWALA ,  Uday CHANDRASEKHAR ,  Purval S. SULE ,  Sagar UPADHYAY

IPC: G11C16/34 ,  G11C16/10 ,  G11C8/06 ,  G11C8/10 ,  G06F11/14

Abstract: A programming of a memory device configurable to reach a plurality of voltage levels is initiated. For each voltage level to be reached, a checkpoint is set up within a sequence of program pulses applied for the programming of the memory device, to determine whether a plurality of memory cells of the memory device have reached the voltage level. The programming of the memory device is aborted, in response to determining at the checkpoint that the plurality of memory cells have not reached the voltage level.