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34 条记录 (耗时 0.022 秒)

    Resource load balancing based on usage and power limits
    14.
    发明授权
    Resource load balancing based on usage and power limits 有权

    公开(公告)号：US10983581B2

    公开(公告)日：2021-04-20

    申请号：US15859598

    申请日：2017-12-31

    申请人： Intel Corporation

    发明人： Sanjeev Jahagirdar ,  Altug Koker ,  Yoav Harel ,  Kenneth Brand ,  Chandra Gurram ,  Eric Finley ,  Bhushan Borole ,  Carlos Nava Rodriguez

    IPC分类号： G06F1/32 ,  G06F1/324 ,  G06F1/3212 ,  G06F1/3234

    摘要： Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.

    GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT
    16.
    发明申请
    GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT 有权

    公开(公告)号：US20230088743A1

    公开(公告)日：2023-03-23

    申请号：US17481448

    申请日：2021-09-22

    申请人： Intel Corporation

    发明人： Supratim Pal ,  Chandra Gurram ,  Fan-Yin Tzeng ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Timothy R. Bauer ,  Vikranth Vemulapalli ,  Wei-Yu Chen

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06T1/20

    摘要： An apparatus to facilitate gathering payload from arbitrary registers for send messages in a graphics environment is disclosed. The apparatus includes processing resources comprising execution circuitry to receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers; decode a first phase of the send gather message instruction; based on decoding the first phase, cause a second phase of the send gather message instruction to bypass an instruction decode stage; and dispatch the first phase subsequently followed by dispatch of the second phase to a send pipeline. The apparatus can also perform an immediate move of the IDs of the plurality of individual registers to an architectural register of the execution circuitry and include a pointer to the architectural register in the send gather message instruction.

    REGISTER FILE FOR SYSTOLIC ARRAY
    17.
    发明申请
    REGISTER FILE FOR SYSTOLIC ARRAY 有权

    公开(公告)号：US20220413851A1

    公开(公告)日：2022-12-29

    申请号：US17304794

    申请日：2021-06-25

    申请人： Intel Corporation

    发明人： Chandra Gurram ,  Wei-yu Chen ,  Fangwen Fu ,  Sabareesh Ganapathy ,  Varghese George ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Mike Macpherson ,  Supratim Pal ,  Jorge Parra

    IPC分类号： G06F9/30 ,  G06F17/16 ,  G06F7/483

    摘要： A processing apparatus includes a general-purpose parallel processing engine including a set of multiple processing elements including a single precision floating-point unit, a double precision floating point unit, and an integer unit; a matrix accelerator including one or more systolic arrays; a first register file coupled with a first read control circuit, wherein the first read control circuit couples with the set of multiple processing elements and the matrix accelerator to arbitrate read requests to the first register file from the set of multiple processing elements and the matrix accelerator; and a second register file coupled with a second read control circuit, wherein the second read control circuit couples with the matrix accelerator to arbitrate read requests to the second register file from the matrix accelerator and limit access to the second register file by the set of multiple processing elements.

    COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING MACHINES USING SYSTOLIC ARRAYS
    20.
    发明申请
    COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING MACHINES USING SYSTOLIC ARRAYS 有权

    公开(公告)号：US20220058158A1

    公开(公告)日：2022-02-24

    申请号：US17518202

    申请日：2021-11-03

    申请人： Intel Corporation

    发明人： Subramaniam Maiyuran ,  Jorge Parra ,  Supratim Pal ,  Chandra Gurram

    IPC分类号： G06F15/80

    摘要： An apparatus to facilitate computing efficient cross channel operations in parallel computing machines using systolic arrays is disclosed. The apparatus includes a plurality of registers and one or more processing elements communicably coupled to the plurality of registers. The one or more processing elements include a systolic array circuit to perform cross-channel operations on source data received from a single source register of the plurality of registers, wherein the systolic array circuit is modified to: receive inputs from the single source register at different stages of the systolic array circuit; perform cross-channel operations at channels of the systolic array circuit; bypass disabled channels of the systolic array circuit, the disabled channels not used to compute the cross-channel operations; and broadcast a final result of a final stage of the systolic array circuit to all channels of a destination register.