公开(公告)号：US20240312909A1

公开(公告)日：2024-09-19

申请号：US18670390

申请日：2024-05-21

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H01L23/498 ,  H03K19/17704

CPC classification number: H01L23/528 ,  H01L23/49816 ,  H03K19/17704

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US12026008B2

公开(公告)日：2024-07-02

申请号：US17973428

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

IPC: G06F1/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: G06F1/10 ,  H01L23/3114 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14515 ,  H01L2224/16227 ,  H01L2224/14515 ,  H01L2924/00012

Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.

公开(公告)号：US12009298B2

公开(公告)日：2024-06-11

申请号：US18137405

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H01L23/498 ,  H03K19/17704

CPC classification number: H01L23/528 ,  H01L23/49816 ,  H03K19/17704

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US11670589B2

公开(公告)日：2023-06-06

申请号：US17131464

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L25/075 ,  H01L33/50 ,  H01L33/54 ,  H01L33/56 ,  H01L33/58 ,  H01L33/62 ,  F21V7/05 ,  F21V7/22 ,  H01L33/60 ,  H01L23/528 ,  H03K19/17704 ,  H01L23/498

CPC classification number: H01L23/528 ,  H01L23/49816 ,  H03K19/17704

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US11580054B2

公开(公告)日：2023-02-14

申请号：US16235608

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  George Chong Hean Ooi

IPC: G06F15/78 ,  G06F13/40 ,  G06F13/16

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

公开(公告)号：US11500412B2

公开(公告)日：2022-11-15

申请号：US16367925

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

IPC: G06F1/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.

公开(公告)号：US20220092009A1

公开(公告)日：2022-03-24

申请号：US17543433

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Lai Guan Tang ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Chee Hak Teh ,  MD Altaf Hossain

IPC: G06F13/20 ,  G06F13/40

Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.

公开(公告)号：US11062070B2

公开(公告)日：2021-07-13

申请号：US16368696

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Lai Guan Tang ,  Chee Hak Teh

IPC: G06F30/34 ,  H01L25/18 ,  H01L23/00 ,  G06F13/20 ,  H04J3/02 ,  G06F115/08

Abstract: Systems or methods of the present disclosure may facilitate meeting connectivity demands between the dies of the modularized integrated circuits. Such an integrated circuit system may include a first die of programmable fabric circuitry that is communicatively coupled to a second die of modular periphery intellectual property (IP) tile via a modular interface. The modular interface may enable communication between a first microbump of the first die and a second microbump of the second die using a time-division multiplexing (TDM) technique. The modular interface may also enable communication between the first microbump and the second microbump using a wire-to-wire connection that does not comprise the TDM technique.

公开(公告)号：US20210111116A1

公开(公告)日：2021-04-15

申请号：US17131464

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H03K19/17704 ,  H01L23/498

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US10936511B2

公开(公告)日：2021-03-02

申请号：US16232834

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Chee Hak Teh

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/28

Abstract: Systems and methods for providing capability of access to distributed memory blocks using a global address scheme in a programmable logic device. Each of the distributed memory blocks includes routing circuitry that receives data, and in a first mode, decodes whether the data is intended for a respective distributed memory block. In a second mode, the data may bypass routing circuitry. Furthermore, the data may be received at the distributed memory block via cascade connections of distributed memory blocks in a column and/or via register in the programmable fabric of the programmable logic device.