公开(公告)号：US11101356B2

公开(公告)日：2021-08-24

申请号：US16641032

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

公开(公告)号：US20210005722A1

公开(公告)日：2021-01-07

申请号：US16641032

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

公开(公告)号：US11735670B2

公开(公告)日：2023-08-22

申请号：US17497864

申请日：2021-10-08

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/161 ,  H01L27/088 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US20230207655A1

公开(公告)日：2023-06-29

申请号：US17561915

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Rushabh D. Shah ,  Glenn Glass ,  Mohammad R. Hasan ,  Anand Murthy ,  Cory C. Bomberger

IPC: H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/456 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/7851

Abstract: Cap layers are formed on silicon germanium (SiGe) source/drain regions to provide etch resistance to processing steps that can occur in a semiconductor manufacturing process between formation of the SiGe source/drain regions and metal contact formation. The cap layers comprise boron and are thin (e.g., 2 nm or less) to provide for a low metal contact resistance. The atomic concentration of boron in the second layer is in a range of about 0.2-20%. In addition to providing etch resistance, the cap layer provides for a thermally stable contact resistance as the cap layer can prevent or limit the creation of voids in the SiGe layer by preventing or limiting the diffusion of germanium from the SiGe layer into the metal in subsequent annealing and other high-temperature processing steps.

公开(公告)号：US20230197716A1

公开(公告)日：2023-06-22

申请号：US17559719

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Cory C. Bomberger ,  Anand Murthy ,  Tahir Ghani ,  Ju Nam ,  Anupama Bowonder

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L21/823412 ,  H01L21/823418

Abstract: An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device comprising: a channel structure including a semiconductor material; a gate stack including a metal, the gate stack on the channel structure; a source structure in a first trench at a first side of the gate stack; a drain structure in a second trench at a second side of the gate stack; individual ones of the source structure and the drain structure including a source or drain (source/drain) liner comprising a doped epitaxial layer conformal with a surface of a corresponding one of the first trench and the second trench; a fill structure filling a portion of a corresponding one the first trench and the second trench, the fill structure adjacent to and compositionally different from the source/drain liner; and metal contact structures coupled to respective ones of the source structure and the drain structure.

公开(公告)号：US20230163212A1

公开(公告)日：2023-05-25

申请号：US17531154

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Cory C. Bomberger ,  Anand Murthy ,  Rushabh D. Shah ,  Sudipto Naskar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: An integrated circuit (IC) device, and a method of forming the same. The IC device includes a transistor device comprising a multilayer stack that has a plurality of channel layers including a semiconductor material; a gate structure wrapped at least partially around the channel layers, the gate structure including a metal; an epitaxial source structure at a first lateral end of the multilayer stack; an epitaxial drain structure at a second lateral end of the multilayer stack opposite the first lateral end; and inner spacers between the gate structure and respective ones of the source structure and the drain structure, wherein at least one of the source structure or the drain structure does not exhibit a pattern of crystallographic defects extending from the inner spacers.

公开(公告)号：US11056592B2

公开(公告)日：2021-07-06

申请号：US16611920

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Karthik Jambunathan ,  Cory C. Bomberger ,  Glenn A. Glass ,  Anand S. Murthy ,  Ju H. Nam ,  Tahir Ghani

IPC: H01L29/78 ,  H01L27/092

Abstract: An integrated circuit (IC) includes a substrate that includes silicon. A first layer is on the substrate and includes a first monocrystalline semiconductor material, the first layer having a plurality of defects. A second layer is on the first layer and includes a second monocrystalline semiconductor material that includes germanium. A strained channel structure is above the first layer. A gate structure is at least above the channel structure. A source region is adjacent the channel structure. A drain region is adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.

公开(公告)号：US20210005748A1

公开(公告)日：2021-01-07

申请号：US16641022

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US20200258982A1

公开(公告)日：2020-08-13

申请号：US16649716

申请日：2017-12-26

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.