公开(公告)号：US10833969B2

公开(公告)日：2020-11-10

申请号：US15655855

申请日：2017-07-20

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Daniel Rivas Barragan ,  John Chun Kwok Leung ,  Suraj Prabhakaran ,  Murugasamy K. Nachimuthu ,  Slawomir Putyrski

IPC: H04L12/26 ,  G06F16/22 ,  G06F16/23 ,  H04L12/24 ,  H04L12/927 ,  H04Q9/00 ,  H04L29/08 ,  H04L12/925

Abstract: Techniques for increasing malleability in software-defined infrastructures are described. A compute node, including one or more processor circuits, may be configured to access one or more remote resources via a fabric, the compute node may be configured to monitor utilization of the one or more remote resources. The compute node may be further configured to identify based on one or more criteria that one or more remote resources may be released and initiate release of identified one or more remote resources. The compute node may be configured to generate a notification to a software stack indicating that the identified one or more remote resources has been released. Other embodiments are described and claimed.

公开(公告)号：US10824358B2

公开(公告)日：2020-11-03

申请号：US15720653

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Murugasamy K. Nachimuthu ,  Daniel Rivas Barragan

IPC: G06F11/00 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L12/24 ,  H04L29/08 ,  G06F11/30 ,  G06F9/50 ,  H03M7/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  G06F9/38 ,  G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/453 ,  H01R13/631 ,  H05K7/14 ,  H04L12/911 ,  G06F11/14 ,  H04L29/06 ,  G06F15/80

Abstract: Technologies for dynamically managing the reliability of disaggregated resources in a managed node include a resource manager server. The resource manager server includes communication circuit to receive resource data from a set of disaggregated resources that indicates reliability of each disaggregated resource of the set of disaggregated resources and a node request to compose a managed node. The resource manager server further includes a compute engine to determine node parameters from the node request indicative of a target reliability of one or more disaggregated resources of the set of disaggregated resources to be included in the managed node, compose a managed node from the set of disaggregated resources that satisfies the node parameters by configuring the compute sled to utilize the disaggregated resources of the managed node for the execution of a workload, and monitor the disaggregated resources of the managed node for a failure.

公开(公告)号：US10785295B2

公开(公告)日：2020-09-22

申请号：US15199572

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Daniel Rivas Barragan ,  Kshitij A. Doshi ,  Mark A. Schmisseur ,  Steen Larsen

IPC: H04L29/08 ,  G06F3/06 ,  H04L12/931

Abstract: Fabric encapsulated resilient storage is hardware-assisted resilient storage in which the reliability capabilities of a storage server are abstracted and managed transparently by a host fabric interface (HFI) to a switch. The switch abstracts the reliability capabilities of a storage server into a level of resilience in a hierarchy of levels of resilience. The resilience levels are accessible by clients as a quantifiable characteristic of the storage server. The resilience levels are used by the switch fabric to filter which storage servers store objects responsive to client requests to store objects at a specified level of resilience.

公开(公告)号：US10680976B2

公开(公告)日：2020-06-09

申请号：US15260638

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez

IPC: H04L12/933 ,  H04L29/10

Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.

公开(公告)号：US10241885B2

公开(公告)日：2019-03-26

申请号：US15460385

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Daniel Rivas Barragan ,  Patrick Lu

IPC: G06F11/34 ,  G06F11/30 ,  H03K19/177

Abstract: In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.

公开(公告)号：US20180284993A1

公开(公告)日：2018-10-04

申请号：US15476875

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan

IPC: G06F3/06 ,  G06F9/54 ,  H04L29/08 ,  G06F9/48 ,  G06F9/45

Abstract: Technology for a controller in a storage area network (SAN) node operable to perform data requests is described. The controller can receive a data request from a remote node. The data request can specify a data payload and a type of operation associated with the data request. The controller can select a kernel from a kernel table stored in the memory based on a set of rules. The kernel can be matched to the data request in accordance with the set of rules. The kernel can be configured using a bit stream. The controller can execute the kernel in order to perform the data request in accordance with the data payload and the type of operation.

公开(公告)号：US20180267878A1

公开(公告)日：2018-09-20

申请号：US15460385

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Daniel Rivas Barragan ,  Patrick Lu

IPC: G06F11/34 ,  G06F11/30 ,  H03K19/177

CPC classification number: G06F11/3409 ,  G06F11/3017 ,  H03K19/1776 ,  H03K19/17764

Abstract: In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.

公开(公告)号：US10038767B2

公开(公告)日：2018-07-31

申请号：US15260613

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

IPC: H04L12/50 ,  H04L29/08 ,  H04L1/16

CPC classification number: H04L69/324 ,  G06F15/173 ,  H04L1/1642 ,  H04L12/50 ,  H04L45/28 ,  H04L45/745 ,  H04L49/00

Abstract: Technologies for using fabric supported sequencers in fabric architectures includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an sequencer access message from one of the plurality of computing nodes that includes an identifier of a sequencing counter corresponding to a sequencer session and one or more operation parameters. The network switch is additionally configured to perform an operation on a value associated with the identifier of the sequencing counter as a function of the one or more operation parameters, increment the identifier of the sequencing counter, and associate a result of the operation with the incremented identifier of the sequencing counter. The network switch is further configured to transmit an acknowledgment of successful access to the computing node that includes the result of the operation and the incremented identifier of the sequencing counter. Other embodiments are described herein.

公开(公告)号：US20180095906A1

公开(公告)日：2018-04-05

申请号：US15283284

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Francesc Guim Bernat ,  Daniel Rivas Barragan

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/1027 ,  G06F13/18 ,  G06F12/14

CPC classification number: G06F13/1663 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0815 ,  G06F12/1027 ,  G06F12/1433 ,  G06F13/18 ,  G06F2212/1052 ,  G06F2212/68

Abstract: Apparatuses, systems, and methods for coherently sharing data across a multi-node network is described. A coherency protocol for such data sharing can include identifying a memory access request from a requesting node for an I/O block of data in a shared I/O address space of a multi-node network, determining a logical ID and a logical offset of the I/O block, identifying an owner of the I/O block, negotiating permissions with the owner of the I/O block, and performing the memory access request on the I/O block.

公开(公告)号：US12204471B2

公开(公告)日：2025-01-21

申请号：US18243493

申请日：2023-09-07

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Daniel Rivas Barragan ,  Kshitij A. Doshi ,  Mark A. Schmisseur

IPC: G06F12/00 ,  C07F15/00 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/1018 ,  G06F13/16 ,  H04L12/46 ,  H04L49/90

Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.