公开(公告)号：US09071528B2

公开(公告)日：2015-06-30

申请号：US13730024

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US20150082091A9

公开(公告)日：2015-03-19

申请号：US14144406

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： David Harriman

IPC: G06F11/07

CPC classification number: G06F13/4282 ,  G06F11/0745 ,  G06F13/4022 ,  H04L29/0653 ,  H04L69/22

Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type.

Abstract translation: 发送装置和接收装置经由计算机系统内的高速串行接口耦合。 发送装置发送包含指示多个消息组中的一个的消息组子字段的消息请求事务的包头。 分组报头还包括指示消息请求分组是否包括数据的格式字段。 分组报头还包括用于指示特定消息类型的消息代码字段。

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US20200183876A1

公开(公告)日：2020-06-11

申请号：US16706637

申请日：2019-12-06

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Anil Vasudevan ,  David Harriman

IPC: G06F13/42 ,  G06F13/40

Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

公开(公告)号：US09049125B2

公开(公告)日：2015-06-02

申请号：US13729953

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US20140304448A9

公开(公告)日：2014-10-09

申请号：US14144309

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F13/40

CPC classification number: G06F13/4068 ,  A47K7/028 ,  G06F13/4273 ,  G06F2213/0026

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US08819306B2

公开(公告)日：2014-08-26

申请号：US13729673

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F13/00

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract translation: 提出了一种增强的通用输入/输出通信架构，协议和相关方法。

公开(公告)号：US20140189174A1

公开(公告)日：2014-07-03

申请号：US14144320

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F13/42

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract translation: 提出了一种增强的通用输入/输出通信架构，协议和相关方法。

公开(公告)号：US20210165756A1

公开(公告)日：2021-06-03

申请号：US17153751

申请日：2021-01-20

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Anil Vasudevan ,  David Harriman

IPC: G06F13/42 ,  G06F13/40

Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

公开(公告)号：US10360171B2

公开(公告)日：2019-07-23

申请号：US14799165

申请日：2015-07-14

Applicant: Intel Corporation

Inventor： David Harriman ,  Jasmin Ajanovic

IPC: G06F13/42 ,  H04L29/06 ,  G06F13/40 ,  G06F11/07

Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal.