公开(公告)号：US20190047579A1

公开(公告)日：2019-02-14

申请号：US15942466

申请日：2018-03-31

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Riccardo Mariani ,  Dean Mulla ,  Robert Gottlieb

IPC: B60W50/023 ,  B60R16/023 ,  B60W50/02

Abstract: Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.

公开(公告)号：US09720491B2

公开(公告)日：2017-08-01

申请号：US14752841

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Dean Mulla ,  Daniel G. Borkowski ,  Krishnakanth V. Sistla ,  Victor Wu ,  Manev Luthra

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0673 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/172

Abstract: Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.

公开(公告)号：US09710041B2

公开(公告)日：2017-07-18

申请号：US14812056

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Krishnakanth V. Sistla ,  Vivek Garg ,  Dean Mulla ,  Ashish V. Choubal ,  Erik G. Hallnor ,  Kimberly C. Weier

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/04 ,  G06F9/38 ,  G06F15/17

CPC classification number: G06F1/3203 ,  G06F1/04 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/38 ,  G06F15/163 ,  G06F15/17 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

公开(公告)号：US20170031412A1

公开(公告)日：2017-02-02

申请号：US14812056

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Krishnakanth V. Sistla ,  Vivek Garg ,  Dean Mulla ,  Ashish V. Choubal ,  Erik G. Hallnor ,  Kimberly C. Weier

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/04 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/38 ,  G06F15/163 ,  G06F15/17 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的核心和耦合到核心的核心周边逻辑。 核心周界逻辑可以包括耦合到核的结构接口逻辑。 反过来，结构接口逻辑可以包括第一存储器，以在核心处于低功率状态时存储核心的状态信息，并且使得耦合在核心和核心之间的管芯间互连能够被维持在活动状态 在核心进入低功率状态期间。 描述和要求保护其他实施例。

公开(公告)号：US09501129B2

公开(公告)日：2016-11-22

申请号：US13780052

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Krishnakanth Sistla ,  Dean Mulla ,  Vivek Garg ,  Mark Rowland ,  Suresh Doraiswamy ,  Ganapati Srinivasa ,  Jeffrey D. Gilbert

IPC: G06F1/32 ,  G06F13/40

CPC classification number: G06F1/324 ,  G06F13/4022 ,  Y02D10/126

Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。 该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。 除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。 该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。 描述和要求保护其他实施例。