公开(公告)号：US11663003B2

公开(公告)日：2023-05-30

申请号：US16452390

申请日：2019-06-25

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Kirk Yap

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30036 ,  G06F9/30167

Abstract: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

公开(公告)号：US10691458B2

公开(公告)日：2020-06-23

申请号：US15716258

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F9/30 ,  H04L9/06

Abstract: A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

公开(公告)号：US10203934B2

公开(公告)日：2019-02-12

申请号：US13631763

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Wajdi K. Feghali ,  Vinodh Gopal ,  James D. Guilford ,  Gilbert Wolrich ,  Kirk S. Yap

IPC: G06F5/06 ,  G06F21/64 ,  H04L9/06 ,  H04L9/32

Abstract: Technologies for executing a serial data processing algorithm on a single variable-length data buffer includes padding data segments of the buffer, streaming the data segments into a data register and executing the serial data processing algorithm on each of the segments in parallel.

公开(公告)号：US09830285B2

公开(公告)日：2017-11-28

申请号：US14882867

申请日：2015-10-14

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09824038B2

公开(公告)日：2017-11-21

申请号：US14882897

申请日：2015-10-14

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09128818B2

公开(公告)日：2015-09-08

申请号：US14286055

申请日：2014-05-23

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract translation: 一般来说，本公开包括具有集成在处理器内的多个可编程单元的装置。 该装置具有将单个地址空间中的地址映射到多个可编程单元内的资源的电路，其中单个地址空间包括针对多个可编程单元中的不同可编程单元中的不同资源的地址，并且其中存在一对一 单个地址空间中的各个地址与多个可编程单元内的资源之间的对应关系。