公开(公告)号：US09577634B2

公开(公告)日：2017-02-21

申请号：US14751060

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H03K19/173 ,  H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0008 ,  H03K19/17704 ,  H03K19/17744

Abstract: Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects.

Abstract translation: 描述了一种装置（例如，路由器），其包括：多个端口; 以及布置成使得至少一个交叉电路接收与多个端口的数据位相关联的所有互连并且可操作以在那些互连上重新路由信号的多个交叉电路电路。

公开(公告)号：US20160182367A1

公开(公告)日：2016-06-23

申请号：US14574106

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Mark A. Anders ,  Gregory K. Chen ,  Himanshu Kaul

IPC: H04L12/721 ,  H04L12/773 ,  H04L12/801 ,  H04L12/933

CPC classification number: H04L45/72 ,  H04L45/16 ,  H04L45/60 ,  H04L47/33 ,  H04L49/109 ,  H04L49/25

Abstract: A first packet and a first direction associated with the first packet are received. The first packet is forwarded to an output port of a plurality of output ports of the first router based on the first direction associated with the first packet. A second direction associated with the first packet is determined. The second direction is based at least on an address of the first packet. The first packet and the second direction are forwarded through the output port of the first router to a second router.

Abstract translation: 接收与第一分组相关联的第一分组和第一方向。 基于与第一分组相关联的第一方向，第一分组被转发到第一路由器的多个输出端口的输出端口。 确定与第一分组相关联的第二方向。 第二方向至少基于第一分组的地址。 第一分组和第二方向通过第一路由器的输出端口转发到第二路由器。

公开(公告)号：US20240232115A1

公开(公告)日：2024-07-11

申请号：US18528509

申请日：2023-12-04

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Gregory K. Chen

IPC: G06F13/40 ,  H04L12/54 ,  H04L49/10

CPC classification number: G06F13/4022 ,  H04L12/54 ,  H04L49/10

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

公开(公告)号：US11663452B2

公开(公告)日：2023-05-30

申请号：US16583217

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram Krishnamurthy ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Deepak Vinayak Kadetotad

IPC: G06F17/16 ,  G06N3/063 ,  G06F7/544 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06F17/16 ,  G06N3/04

Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i−1 layer of the binary neural network.

公开(公告)号：US11281963B2

公开(公告)日：2022-03-22

申请号：US15276111

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： Raghavan Kumar ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Phil Knag

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.

公开(公告)号：US11138499B2

公开(公告)日：2021-10-05

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Jack T. Kavalieros ,  Ian A. Young ,  Sasikanth Manipatruni ,  Ram Krishnamurthy ,  Uygar Avci ,  Gregory K. Chen ,  Amrita Mathuriya ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Nazila Haratipour ,  Van H. Le

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419 ,  G11C11/409 ,  G11C11/22

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US11061646B2

公开(公告)日：2021-07-13

申请号：US16147004

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Phil Knag ,  Gregory K. Chen ,  Raghavan Kumar ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G06F7/544 ,  G11C8/10 ,  G11C8/08 ,  G11C7/12 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/56 ,  G11C11/4091 ,  G06G7/16 ,  G11C11/419

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

公开(公告)号：US20180189645A1

公开(公告)日：2018-07-05

申请号：US15394897

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/0635 ,  G06N3/0445 ,  G06N3/049 ,  G06N3/063

Abstract: In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.

公开(公告)号：US20180089557A1

公开(公告)日：2018-03-29

申请号：US15276111

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： Raghavan Kumar ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Phil Knag

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.

公开(公告)号：US09680459B2

公开(公告)日：2017-06-13

申请号：US14567987

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H03L7/00 ,  H03K5/135 ,  G11C8/18 ,  G11C19/28 ,  G06F5/10 ,  H03K5/00

CPC classification number: H03K5/135 ,  G06F5/10 ,  G11C8/18 ,  G11C19/287 ,  H03K2005/00013

Abstract: A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.