公开(公告)号：US11422615B2

公开(公告)日：2022-08-23

申请号：US16741215

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe Fiat ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3206

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US20210311538A1

公开(公告)日：2021-10-07

申请号：US17347474

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Shravan Kumar Belagal Math ,  Noor Mubeen ,  Harinarayanan Seshadri

IPC: G06F1/324 ,  G06N20/00

Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

公开(公告)号：US20200272219A1

公开(公告)日：2020-08-27

申请号：US16741215

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe FIAT ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US20180059766A1

公开(公告)日：2018-03-01

申请号：US15678025

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/32 ,  G06F9/52 ,  G06F9/30

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

公开(公告)号：US09829963B2

公开(公告)日：2017-11-28

申请号：US14583296

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nithish Mahalingam ,  Rushikesh S. Kadam ,  Vishwesh M. Rudramuni ,  Sujith Thomas

IPC: G06F9/46 ,  G06F1/00 ,  G06F1/32 ,  G06F9/50 ,  G06F1/28

CPC classification number: G06F1/329 ,  G06F1/28 ,  G06F1/3206 ,  G06F9/5094 ,  Y02D10/24

Abstract: Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.

公开(公告)号：US20140258749A1

公开(公告)日：2014-09-11

申请号：US14128945

申请日：2012-11-27

Applicant: INTEL CORPORATION

Inventor： Ren Wamg ,  Tsung-Yuan C. Tai ,  Jr-Shian Tsai ,  Bruce L. Fleming ,  Rajeev D. Muralidhar ,  Mesut A. Ergin ,  Prakash N. Iyer ,  Harinarayanan Seshadri

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

Abstract: Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.

Abstract translation: 系统和方法可以提供用于识别与平台的活动工作负载相关联的运行时间信息，以及至少部分地基于运行时信息来为该平台进行主动空闲状态确定。 此外，平台上的共享资源的低功率状态可以至少部分地基于主动空闲状态确定与主动工作负载的执行同时被控制。

公开(公告)号：US20230004209A1

公开(公告)日：2023-01-05

申请号：US17879635

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe FIAT ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US11132046B2

公开(公告)日：2021-09-28

申请号：US16650782

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Barnes Cooper ,  Harinarayanan Seshadri ,  Rajeev Muralidhar ,  Noor Mubeen

IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/329 ,  G06F1/3296

Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

公开(公告)号：US11036275B2

公开(公告)日：2021-06-15

申请号：US16369643

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Shravan Kumar Belagal Math ,  Noor Mubeen ,  Harinarayanan Seshadri

IPC: G06F1/00 ,  G06F1/324 ,  G06N20/00 ,  G06F17/16 ,  G06F1/3203

Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

公开(公告)号：US09934048B2

公开(公告)日：2018-04-03

申请号：US15084268

申请日：2016-03-29

Applicant: INTEL CORPORATION

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri

IPC: G06F1/00 ,  G06F9/44 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F9/4411 ,  G06F1/263 ,  G06F1/3212 ,  G06F9/4418

Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.