公开(公告)号：US20240105508A1

公开(公告)日：2024-03-28

申请号：US17935647

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Jitendra Kumar Jha ,  Justin Mueller ,  Nazila Haratipour ,  Gilbert W. Dewey ,  Chi-Hing Choi ,  Jack T. Kavalieros ,  Siddharth Chouksey ,  Nancy Zelick ,  Jean-Philippe Turmaud ,  I-Cheng Tung ,  Blake Bluestein

IPC: H01L21/768 ,  H01L29/49

CPC classification number: H01L21/76856 ,  H01L21/76837 ,  H01L21/76877 ,  H01L29/4908

Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.

公开(公告)号：US20240006533A1

公开(公告)日：2024-01-04

申请号：US17856982

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Matthew V. Metz ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/78 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L29/167

Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Boride, indium, or gallium metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting contact metal diffusion into source/drain regions.

公开(公告)号：US09029835B2

公开(公告)日：2015-05-12

申请号：US13721759

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Benjamin Chu-King ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Nitika Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L29/06

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

Abstract translation: 本发明的实施例包括外延层，其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线，翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线，鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部，底部和侧壁的“全面的栅极”结构。 本文描述了其它实施例。