公开(公告)号：US20250028675A1

公开(公告)日：2025-01-23

申请号：US18791963

申请日：2024-08-01

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  SELVAKUMAR PANNEER ,  SAURABH TANGRI ,  BEN ASHBAUGH ,  SCOTT JANUS ,  ABHISHEK APPU ,  VARGHESE GEORGE ,  RAVISHANKAR IYER ,  NILESH JAIN ,  PATTABHIRAMAN K ,  ALTUG KOKER ,  MIKE MACPHERSON ,  JOSH MASTRONARDE ,  ELMOUSTAPHA OULD-AHMED-VALL ,  JAYAKRISHNA P. S ,  ERIC SAMSON

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US20220122215A1

公开(公告)日：2022-04-21

申请号：US17428216

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  SELVAKUMAR PANNEER ,  SAURABH TANGRI ,  BEN ASHBAUGH ,  SCOTT JANUS ,  ABHISHEK APPU ,  VARGHESE GEORGE ,  RAVISHANKAR IYER ,  NILESH JAIN ,  PATTABHIRAMAN K ,  ALTUG KOKER ,  MIKE MACPHERSON ,  JOSH MASTRONARDE ,  ELMOUSTAPHA OULD-AHMED-VALL ,  JAYAKRISHNA P. S ,  ERIC SAMSON

IPC: G06T1/60 ,  G06F12/06 ,  G06F12/1009 ,  G06T1/20 ,  G06F12/0875 ,  G06F9/38

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US20180314887A1

公开(公告)日：2018-11-01

申请号：US15582106

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： CARL S. MARSHALL ,  RAVISHANKAR IYER ,  SEJUN KIM ,  DOYE C. EMELUE

IPC: G06K9/00 ,  G06K9/20

Abstract: Methods, apparatus, and system to enable and implement interaction between a computer device and a person (or people) such as via images and objects identified in such images. The interaction may make possible rapid and convenient machine learning with respect to such objects.

公开(公告)号：US20170269906A1

公开(公告)日：2017-09-21

申请号：US15070988

申请日：2016-03-15

Applicant: Intel Corporation

Inventor： GLEN J. ANDERSON ,  REBECCA A. CHIERICHETTI ,  MENG SHI ,  YEVGENIY Y. YARMOSH ,  MARK R. FRANCIS ,  RAVISHANKAR IYER ,  REESE BOWES ,  ANKUR AGRAWAL

IPC: G06F9/44

CPC classification number: G06F8/24 ,  G06F17/50

Abstract: Apparatuses, methods and storage medium associated with a model compute system for physical programming are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify first rules associated with one or more physical subcomponents, e.g., blocks, tiles, or the like, or combinations thereof, assembled in a constructed model in a first control modality, wherein at least one first rule defines a first predetermined behavior of the constructed model, and determine a first program stack for execution by the model compute system based on the first rules associated with the one or more physical subcomponents. Other embodiments may be described and/or claimed.

公开(公告)号：US20160306630A1

公开(公告)日：2016-10-20

申请号：US15194558

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： ZHEN FANG ,  XIAOWEI JIANG ,  SRIHARI MAKINENI ,  RAMESHKUMAR G. ILLIKKAL ,  RAVISHANKAR IYER

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/327 ,  G06F9/3861 ,  G06F9/4806 ,  G06F9/4812 ,  G06F13/24

Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

公开(公告)号：US20160299849A1

公开(公告)日：2016-10-13

申请号：US14680287

申请日：2015-04-07

Applicant: Intel Corporation

Inventor： ANDREW J. HERDRICH ,  EDWIN VERPLANKE ,  RAVISHANKAR IYER ,  CHRISTOPHER C. GIANOS ,  JEFFREY D. CHAMBERLAIN ,  RONAK SINGHAL ,  JULIUS MANDELBLAT ,  BRET L. TOLL

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/604

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Abstract translation: 具有代码和数据优先级的缓存分配的系统和方法。 示例系统可以包括：高速缓存; 处理核心，可操作地耦合到高速缓存; 以及高速缓存控制逻辑，响应于接收到包括请求类型的标识符和服务等级的标识符的高速缓存填充请求，以识别对应于与请求类型和类别相关联的容量位掩码的高速缓存的子集 的服务。

公开(公告)号：US20160070963A1

公开(公告)日：2016-03-10

申请号：US14477595

申请日：2014-09-04

Applicant: Intel Corporation

Inventor： SHAYOK CHAKRABORTY ,  OMESH TICKOO ,  RAVISHANKAR IYER

IPC: G06K9/00 ,  G11B27/30 ,  G11B20/10

CPC classification number: G06K9/00751 ,  G06K9/6271 ,  G06K2209/27 ,  G11B20/10527 ,  G11B27/30 ,  G11B2020/10537 ,  H04N21/41407 ,  H04N21/4223 ,  H04N21/44008 ,  H04N21/8456 ,  H04N21/8549

Abstract: System, apparatus, method, and computer readable media for on-the-fly captured video summarization. A video stream is incrementally summarized in concurrence with generation of the stream by a camera module. Saliency of the video stream summary is maintained as the stream evolves by updating the summary to include only the most significant frames. In one exemplary embodiment, saliency is determined by optimizing an objective function including terms that are indicative of both the diversity of a selection, and how representative the selection is to the processed portion of the video data corpus. A device platform including a CM and comporting with the exemplary architecture may provide video camera functionality at ultra-low power, and/or with ultra-low storage resources, and/or with ultra-low communication channel bandwidth.

Abstract translation: 用于即时拍摄的视频摘要的系统，装置，方法和计算机可读介质。 通过相机模块生成流，逐渐概括出视频流。 通过更新摘要以仅包括最重要的帧，随着流的演进，视频流摘要的显着性将得到保持。 在一个示例性实施例中，通过优化目标函数来确定显着性，所述目标函数包括指示选择的多样性的项，以及对视频数据语料库的处理部分的选择的代表性。 包括CM和与示例性架构相结合的设备平台可以以超低功率和/或超低存储资源和/或具有超低通信信道带宽提供视频摄像机功能。