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    Changing cache ownership in clustered multiprocessor
    11.
    发明授权
    Changing cache ownership in clustered multiprocessor 有权

    公开(公告)号：US09690706B2

    公开(公告)日：2017-06-27

    申请号：US14668831

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

    IPC: G06F12/08 ,  G06F12/084

    CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

    Abstract: Resolving coherency issues inherent in sharing distributed cache is described. A chip multiprocessor may include at least first and second processing clusters, each having multiple cores of a processor, multiple cache slices co-located with the multiple cores, and a memory controller (MC). The processor stores directory information in a memory coupled to the processor to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space, the processor may remap first lines of first cache slices, corresponding to the first address space, to second lines in second cache slices of the second cluster, and update the directory information (e.g., a state of the first cache lines) to change the cluster cache ownership of the first address space to the second cluster. One of the MCs may manage such updating of the directory.

    Early wake-warn for clock gating control
    12.
    发明授权
    Early wake-warn for clock gating control 有权
    提前唤醒时钟门控控制

    公开(公告)号：US09552308B2

    公开(公告)日：2017-01-24

    申请号：US14126919

    申请日：2013-09-30

    Applicant: Intel Corporation

    Inventor： Suresh Sugumar ,  Mahesh K. Kumashikar ,  Rahul Pal ,  Sridhar Muthrasanallur

    IPC: G06F13/00 ,  G06F13/42 ,  G06F9/46

    CPC classification number: G06F13/00 ,  G06F1/3206 ,  G06F9/46 ,  G06F13/4273 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A request associated with a particular cache record is generated to be sent to a system component associated with a cache bank over an interconnect. A wake-warn signal is sent over a dedicated wake-warn channel to indicate to the system component that the request is to arrive. Wake-warn signals cause a disabled clock to be ungated to an enabled state. The request is then sent to the system component.

    Abstract translation: 生成与特定高速缓存记录相关联的请求，以通过互连发送到与高速缓存组相关联的系统组件。 唤醒警告信号通过专用的唤醒通道发送，以向系统组件指示请求到达。 唤醒信号导致禁用的时钟被禁止到启用状态。 然后将请求发送到系统组件。

    Mission-critical computing architecture
    14.
    发明授权
    Mission-critical computing architecture 有权

    公开(公告)号：US10514990B2

    公开(公告)日：2019-12-24

    申请号：US15823313

    申请日：2017-11-27

    Applicant: Intel Corporation

    Inventor： Bahaa Fahim ,  Swadesh Choudhary ,  Rahul Pal ,  Vedaraman Geetha

    IPC: G06F11/20 ,  G06F11/18 ,  G06F11/14 ,  G06F9/38

    Abstract: Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

    MISSION-CRITICAL COMPUTING ARCHITECTURE
    15.
    发明申请
    MISSION-CRITICAL COMPUTING ARCHITECTURE 审中-公开

    公开(公告)号：US20190163583A1

    公开(公告)日：2019-05-30

    申请号：US15823313

    申请日：2017-11-27

    Applicant: Intel Corporation

    Inventor： Bahaa Fahim ,  Swadesh Choudhary ,  Rahul Pal ,  Vedaraman Geetha

    IPC: G06F11/16 ,  G06F11/14 ,  G06F11/18

    Abstract: Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

    Branch Predictor with Empirical Branch Bias Override
    16.
    发明申请
    Branch Predictor with Empirical Branch Bias Override 有权

    公开(公告)号：US20180173533A1

    公开(公告)日：2018-06-21

    申请号：US15383832

    申请日：2016-12-19

    Applicant: Intel Corporation

    Inventor： Niranjan K. Soundararajan ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan

    IPC: G06F9/38

    Abstract: A processor may include a baseline branch predictor and an empirical branch bias override circuit. The baseline branch predictor may receive a branch instruction associated with a given address identifier, and generate, based on a global branch history, an initial prediction of a branch direction for the instruction. The empirical branch bias override circuit may determine, dependent on a direction of an observed branch direction bias in executed branch instruction instances associated with the address identifier, whether the initial prediction should be overridden, may determine, in response to determining that the initial prediction should be overridden, a final prediction that matches the observed branch direction bias, or may determine, in response determining that the initial prediction should not be overridden, a final prediction that matches the initial prediction. The predictor may update an entry in the global branch history reflecting the resolved branch direction for the instruction following its execution.

    Changing cache ownership in clustered multiprocessor
    17.
    发明授权
    Changing cache ownership in clustered multiprocessor 有权

    公开(公告)号：US09940238B2

    公开(公告)日：2018-04-10

    申请号：US15602603

    申请日：2017-05-23

    Applicant: INTEL CORPORATION

    Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

    IPC: G06F12/08 ,  G06F12/084

    CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

    Abstract: A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.

    Hardware lockstep checking within a fault detection interval in a system on chip
    20.
    发明授权
    Hardware lockstep checking within a fault detection interval in a system on chip 有权

    公开(公告)号：US10831628B2

    公开(公告)日：2020-11-10

    申请号：US16218078

    申请日：2018-12-12

    Applicant: Intel Corporation

    Inventor： Umberto Santoni ,  Rahul Pal ,  Philip Abraham ,  Mahesh Mamidipaka ,  C Santhosh

    IPC: G06F11/273 ,  G06F11/16 ,  G06F11/10

    Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

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