公开(公告)号：US10324724B2

公开(公告)日：2019-06-18

申请号：US14971904

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Patrick P. Lai ,  Tyler N. Sondag ,  Sebastian Winkel ,  Polychronis Xekalakis ,  Ethan Schuchman ,  Jayesh Iyer

IPC: G06F9/30

Abstract: Methods and apparatuses relating to a fusion manager to fuse instructions are described. In one embodiment, a hardware processor includes a hardware binary translator to translate an instruction stream into a translated instruction stream, a hardware fusion manager to fuse multiple instructions of the translated instruction stream into a single fused instruction, a hardware decode unit to decode the single fused instruction into a decoded, single fused instruction, and a hardware execution unit to execute the decoded, single fused instruction.

公开(公告)号：US20190042247A1

公开(公告)日：2019-02-07

申请号：US15905623

申请日：2018-02-26

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison Collins ,  Sebastian Winkel ,  Howard Chen

IPC: G06F9/30

Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

公开(公告)号：US10083033B2

公开(公告)日：2018-09-25

申请号：US14643855

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Sebastian Winkel ,  Girish Venkatasubramanian ,  Tyler N. Sondag ,  Rolf Kassa

IPC: G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

Abstract: A method and apparatus are described for efficient register reclamation. For example, one embodiment of an apparatus comprises: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.

公开(公告)号：US20160328239A1

公开(公告)日：2016-11-10

申请号：US14704108

申请日：2015-05-05

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30112 ,  G06F11/1056

Abstract: In one embodiment, a processor includes logic, responsive to a first instruction, to perform an operation on a first source operand and a second source operand associated with the first instruction and write a result of the operation to a destination location comprising a third source operand. The write may be a partial write of the destination location to maintain an unmodified portion of the third source operand. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括响应于第一指令的逻辑，以对与第一指令相关联的第一源操作数和第二源操作数执行操作，并将操作的结果写入到包括第三源操作数的目的位置 。 写入可以是目的地位置的部分写入，以维持第三源操作数的未修改部分。 描述和要求保护其他实施例。

公开(公告)号：US09274799B1

公开(公告)日：2016-03-01

申请号：US14494829

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

IPC: G06F9/45 ,  G06F9/38

CPC classification number: G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

Abstract: A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

Abstract translation: 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的逻辑，以及基于所确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的逻辑，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。

公开(公告)号：US20230315501A1

公开(公告)日：2023-10-05

申请号：US17711770

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Rangeen Basu Roy Chowdhury ,  Matthew C. Merten ,  Jason M. Agron ,  Tyler N. Sondag ,  Gregory A. Woods

IPC: G06F9/455

CPC classification number: G06F9/4552 ,  G06F9/45525

Abstract: Systems, methods, and devices for original code emulation for performance monitoring is provided. A system may memory to store instructions. A processor may implement an instruction converter in hardware or software to convert the instructions to translated code. Specifically, the instruction converter receives the instructions and translates the stored instructions into the translated code that includes one or more indexed instructions. The one or more indexed instructions include a field indicating a number of branches in the stored instructions that are taken in the translated code.

公开(公告)号：US20230102562A1

公开(公告)日：2023-03-30

申请号：US17053531

申请日：2019-11-06

Applicant: Intel Corporation

Inventor： Junyong Ding ,  Mohammad Haghighat ,  Qi Zhang ,  Sebastian Winkel ,  Tianyou Li

IPC: G06F8/41

Abstract: Systems, apparatuses and methods may provide for developer stage technology that embeds binary code into an application binary file, wherein the binary code corresponds to vector functions and non-vector functions in statically typed source code, and generates intermediate representation (IR) data, wherein the intermediate representation data corresponds to the vector functions in the statically typed source code. Additionally, the developer stage technology embeds the IR data in the application binary file. Moreover, deployment stage technology may generate a first compilation output based on the application binary file and detect a capability change in an execution environment associated with the first compilation output. The deployment stage technology may also generate, in response to the detected capability change, a second compilation output based on the first compilation output.

公开(公告)号：US20190179766A1

公开(公告)日：2019-06-13

申请号：US15839310

申请日：2017-12-12

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jason M. Agron ,  Cristiano Pereira ,  Glenn Hinton ,  Sebastian Winkel ,  Rangeen Basu Roy Chowdhury

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F9/30

Abstract: A processor comprising an instruction execution circuit to execute a translated code generated based on a received code and a translation table (TT) controller circuit coupled to a translation table comprising a plurality of address mappings, wherein the TT controller circuit is to identify a trigger event associated with a physical memory page, determine, based on an identifier of the physical memory page, an entry in a manifest table, the entry comprising an address mapping between a first memory address within an address range comprising the physical memory page and a second memory address, and store the address mapping to the translation table.

公开(公告)号：US09996356B2

公开(公告)日：2018-06-12

申请号：US14998299

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Jason M. Agron ,  Ethan Schuchman ,  Sebastian Winkel ,  Youfeng Wu ,  Gisle Dankel

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30185 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3865

Abstract: Apparatus and method for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.

公开(公告)号：US20180095761A1

公开(公告)日：2018-04-05

申请号：US15281957

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Jamison D. Collins ,  Tyler Sondag

IPC: G06F9/30 ,  G06F3/06

CPC classification number: G06F9/30043 ,  G06F3/0608 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3812 ,  G06F9/382

Abstract: A processing device includes a store instruction identification unit to identify a pair of store instructions among a plurality of instructions in an instruction queue. The pair of store instructions include a first store instruction and a second store instruction. The first data of the first store instruction corresponds to a first memory region adjacent to a second memory region, and a second data of the second store instruction corresponds to the second memory region. The processing device to include a store instruction fusion unit to fuse the first store instruction with the second store instruction resulting in a fused store instruction.